Front End Of Line Research Articles

(Invited) Understanding Self-Heating in FinFETS and Its Impact on Metal Interconnect

Self-Heating (SE) in FinFETs can be of significant concern for reliability of back-end-of-line (BEOL) interconnects due to electromigration (FM) failure, which is a highly sensitive degradation mechanism at elevated temperatures (1, 2). Temperature levels of ≥5°C due to front-end-of-line (FEOL) self-heating at M1 lines can impact the circuit’s reliable operation (3). The confined heat due to self-heating in FinFETS can flow vertically and laterally to the local interconnects and increasing the metal temperature thereby accelerating the EM failure rate probability. Furthermore, while FinFETs provide the performance, power and scaling advantages over planar devices the local self-heating can potentially affect device performance and exacerbate the effects of various reliability mechanisms (4). It is, therefore, imperative to understand the quantification of self-heating in FinFETs and its reliability implications in the devices, circuits and metal interconnects.In this presentation we will discuss several experimental methodologies to quantify SH using wafer level measurements by implementing three different types of electrical sense elements. The sensing schemes evaluate the surround heat sensing using the electrical characteristic of a neighboring FET device and a local heat sensing element using a 4-terminal kelvin contact to measure the thermal coefficient of resistance of the metal gate. We will evaluate the proximity and effectiveness of these sense elements. We will also investigate the impact of SH on logic circuits using a simple ring-oscillator circuit. The characteristics will be validated through predictive thermal simulations. From the results it is inferred that dense circuit applications such as clock buffers are required to be studied more carefully for its impact of self-heating on upper metal lines. This is particularly critical for technologies such as SOI FinFETs where heat generated by frontend-of-line devices is being forced through the upper metal lines due to the buried oxide where self-heating impact is 5x higher compared to bulk FinFET technology.The author acknowledges the collaborators of Globalfoundries, especially Dr. Peter Paliwoda, for the technical discussion.References W. Chang, S.E. Liu, B.L. Lin, C.C. Chiu, Y.-H. Lee and K. Wu, IEEE IRPS, 2F.6.1, (2015).S-W. Yoo, H. Kim, M. Kang, and H. Shin, of Semicon. Tech and Sc, vol.16(2), 204, (2016).Peter Paliwoda, Doctoral Dissertation, https://digitalcommons.njit.edu/dissertations/1389, NJIT, 1389, pp. 96, (2018).Paliwoda, Z. Chbili, A. Kerber, T. Nigam, K. Nagahiro, S. Cimino, M. Toledano-Luque, L. Pantisano, B.W. Min, and D. Misra, IEEE Trans. on Dev. and Mat. Reliability, vol. 19(2) (2019).

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- k (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

(Invited) Materials and Process Technologies for Scaling BEOL Interconnects

Historically, complementary metal-oxide-semiconductor (CMOS) technology was driven by geometrical scaling of the front-end-of-line (FEOL) transistor but it has slowed down significantly in recent years. On the other hand, back-end-of-line (BEOL) interconnects are projected to continue scaling aggressively to meet power, performance and area targets in advanced nodes. In this paper, we will introduce and review BEOL interconnect options targeting sub-7nm metal pitch with an emphasis on materials and process technologies.

Process-Induced ReRAM Performance Improvement of Atomic Layer Deposited HfO2 for Analog In-Memory Computing Applications

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications.A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing.In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage.References Kuzum et al., Nanotechnology, 24, 382001 (2013)W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

Materials to Systems Co-Optimization Platform for Rapid Technology Development Targeting Future Generation CMOS Nodes

Design technology co-optimization (DTCO) has been a workhorse in optimizing logic technology innovations for a few generations now. With increased complexity associated with each new node and the growing number of technological innovations, it is time to expand the conventional DTCO flows. In this article, we present a novel materials to systems co-optimization (MSCO) platform, expanding the boundaries of traditional DTCO to encompass materials modeling to all the way to system design. To demonstrate the application of our MSCO platform, we discuss various front-end-of-line (FEOL) and middle-of-line (MOL)/back-end-of-line (BEOL) technologies and show their impact on device and circuit performance.

A Review on Chemical Mechanical Planarization of Barrier Layer Metals

Chemical mechanical planarization (CMP) is recognized to be one of the finest polishing techniques which provides a smooth and globally planarized metal surface in the field of semiconductor device manufacturing. This process aids in material removal followed with a well finished and planarized surface by a combination of both chemical and mechanical action imparted by oxidizer and abrasive particle respectively. Semiconductor device manufacturing process is an amalgamation of two sub processes i.e. front end of line (FEOL) and back end of line (BEOL). The whole process consists of different segments comprising of several types of material that need to be planarized. The slurry components play an imperative role in metal CMP. It comprises abrasive, oxidizer, and several additives such as complexing agent, corrosion inhibitor, pH adjustor, slurry stabilizer, etc. and each imparts diverse impact on the material needs to be polished. One of the main topics of concern in this area is the removal rate selectivity of interconnects metal to the barrier layer metal. Thus, the reported review work efforts to emphasize the planarization of barrier layer materials, the various key ingredients employed in metal CMP and removal rate selectivity between interconnects and barrier layer metal.

How good are 2D transistors? An application-specific benchmarking study

The research community has invested heavily in semiconducting two-dimensional (2D) materials, such as transition metal dichalcogenides (TMDs). Their stability when scaled down to a few atoms thick makes them attractive candidates to replace or supplement silicon in many future technologies. Although this sentiment is prevalent, demonstrations of 2D field-effect transistors (FETs) often do not present their data in a way that enables a straightforward comparison. For example, some papers solely use mobility as the figure of merit, while others focus on unnormalized device on-current. Here, we benchmark the performance of a selection of 2D FETs with field-corrected metrics that allow a more accurate projection of their potential; while the demonstrated methods are by no means comprehensive, they provide insight into improved benchmarking of 2D FETs going forward. Importantly, we show that appropriate benchmarking requires consideration of the specific application, with the three dominant potential application areas of front-end-of-line (FEOL) high-performance FETs, back-end-of-line (BEOL) 3D-integrated FETs, and low-cost thin-film FETs (or TFTs) each demonstrated. We find that 2D materials have the potential to compete with silicon as the channel in scaled FEOL high-performance devices. Meanwhile, in BEOL applications, FETs from in situ synthesized 2D materials have performance limited by their low crystal quality – a result of the stringent thermal budget of BEOL fabrication, which necessitates the use of transferred 2D materials. In the TFT area, 2D materials are simpler to fabricate than their silicon-based counterparts and they are competitive with other material alternatives. As promising as these findings are, there remain many hurdles for 2D materials to overcome, including poor reliability, performance variability, and fabrication scalability. Continuous research effort, combined with appropriate benchmarking, is strongly encouraged.

Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.

Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry.

Mapping of integrated PIN diodes with a 3D architecture by scanning microwave impedance microscopy and dynamic spectroscopy.

This work addresses the need for a comprehensive methodology for nanoscale electrical testing dedicated to the analysis of both “front end of line” (FEOL) (doped semiconducting layers) and “back end of line” (BEOL) layers (metallization, trench dielectric, and isolation) of highly integrated microelectronic devices. Based on atomic force microscopy, an electromagnetically shielded and electrically conductive tip is used in scanning microwave impedance microscopy (sMIM). sMIM allows for the characterization of the local electrical properties through the analysis of the microwave impedance of the metal–insulator–semiconductor nanocapacitor (nano-MIS capacitor) that is formed by tip and sample. A highly integrated monolithic silicon PIN diode with a 3D architecture is analysed. sMIM measurements of the different layers of the PIN diode are presented and discussed in terms of detection mechanism, sensitivity, and precision. In the second part, supported by analytic calculations of the equivalent nano-MIS capacitor, a new multidimensional approach, including a complete parametric investigation, is performed with a dynamic spectroscopy method. The results emphasize the strong impact, in terms of distinction and location, of the applied bias on the local sMIM measurements for both FEOL and BEOL layers.

Intelligent MOL(Middle-Of-Line) Design Methodology for 3D FinFET Manufacturability

This research is an outstanding first study on the intelligent design methodology of the core MOL scheme. It can maximize the manufacturability of 3D FinFET technology that is mainly used for foundry AP products ranging from 10nm to 5nm.In order to realize various MOL structures, 3D virtual process simulation considering plasma and surface reaction was implemented, and based on this, the generation of gate to contact short, a chronic defect in FinFET MOL scheme, could be detected without decap. Futhermore, for the feature selection, the process factor sensitivity analysis was performed with the Monte carlo algorithm, which is one of the representative reinforcement learning techniques, and it was found that the key factors of defect were gate to contact misalign and contact etch angle. In the Gate-to-Contact 3D minimum distance probability distribution function generated by millions of samplings based on this intelligent algorithm, the failure criteria can be obtained by mapping with the number of fail bits detected in the wafer.As the device's scaling limit was reached, SCE-driven FEOL(Front-End-Of-Line) characteristics as well as the MOL parasitics' portion became very huge in the 10 nm or less FinFET technology, but all studies have been limited to the effects of device performance via RC(Resistance-Capacitance) analysis.On the other hand, our methodology provides a 3D minimum distance 5.7nm specification for a defect-free MOL structure for the first time, and provides conditions to meet Gate to CNT short zero at the current process capability level when improving M/A 4.5nm and etch ang 1.5o. In silicon, the same result was obtained as predicted. Figure 1

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation

Split manufacturing of integrated circuits means to delegate the front-end-of-line (FEOL) and back-end-of-line (BEOL) parts to different foundries, in order to prevent overproduction, intellectual property (IP) piracy, or targeted insertion of hardware Trojans (i.e., threats arising from adversaries in the FEOL foundry). This article challenges the security promise of split manufacturing by formulating various layout-level placement and routing hints as vector-based and image-based features that enable a sophisticated deep neural network (DNN), which can infer the missing BEOL connections with high accuracy. Compared with the network-flow attack (Wang et al. , 2018), we achieve on average $1.21 \times $ and $1.12 \times $ of their correct connection rate (CCR; the higher, the better) when splitting after M1 and M3, respectively, with less than 1% of their runtime (across the same set of ISCAS-85 and ITC-99 benchmarks). Compared with Zeng et al. (2019), ours reduces the candidate list (the smaller, the better) by 47% with only 1% loss of accuracy, and we further achieve an average CCR of $2.2 \times $ of that of Zeng et al. (2019). Aside from these superior results, we propose a randomized, routing-blockage-centric defense strategy to escalate the resilience against our and other attacks. Our defense strategy, which can be integrated into any commercial design flow, leads on average to $22.78~pp$ (percentage points) degradation in CCR when compared with unprotected layouts, while inducing only 3.3% and 3.2% overheads on power and timing, respectively, within the same die outlines (i.e., zero area cost). The source code of our heterogeneous feature extraction is available at https://github.com/cuhk-eda/split-extract , and the source code of our DNN is available at https://github.com/cuhk-eda/split-attack .

CMOS-Compatible Silicon Photonic Sensor for Refractive Index Sensing Using Local Back-Side Release

Silicon photonic sensors are promising candidates for lab-on-a-chip solutions with versatile applications and scalable production prospects using complementary metal-oxide semiconductor (CMOS) fabrication methods. However, the widespread use has been hindered because the sensing area adjoins optical and electrical components making packaging and sensor handling challenging. In this work, a local back-side release of the photonic sensor is employed, enabling a separation of the sensing area from the rest of the chip. This approach allows preserving the compatibility of photonic integrated circuits in the front-end of line and metal interconnects in the back-end of line. The sensor is based on a micro-ring resonator and is fabricated on wafer-level using a CMOS technology. We revealed a ring resonator sensitivity for homogeneous sensing of 106 nm/RIU.

Spatial Revelations of Chemical and Electrochemical Kinetics into Defect Generations during Semiconductor Processing

Semiconductor processing is an extreme challenge due to the defect generations at a microscopic scale down to nanometers in size. Over the past several decades, the industry has been constantly experiencing dramatically increased complexities in manufacturing. A production flow is often made up of hundreds of steps and involves a variety of complicated equipment and chemicals. In addition to the common three states (i.e., solid, liquid, gas), plasma has also been extensively used in many steps involved in clean, deposition, and etch. Meanwhile, a lot of incidental events and sources, such as contaminations and problem tools, can readily occur from time to time. The list goes on and on. Consequently, some of these detrimental factors and variances can generate various defects in degrading or even crashing production lines.When a defectivity issue occurs, a failure analysis (FA) is typically initiated for identifying the nature of defects and where and how they are embedded into the device stack. To start with, a voltage or current has to be applied to excite the defective spot for detecting a localized thermal or photonic signal. However, a small voltage application or current injection, even in nano-ampere, can easily destroy a microscopic defect. A subsequent cross-sectioning or delayering, even with great care, may miss the defect. Therefore, to nondestructively visualize defects has been a daunting task, and often concludes with a disappointment. Furthermore, the source or origin of an issue may need to be narrowed down by analyzing big data from many production lots and/or further confirmed by executing several designs of experiments (DOEs). All these steps towards root-cause clarification and process improvement can be time-consuming and costly. In addition, the process interactions among different steps can further weaken or cause inconsistencies to the correlations under extensive reviews.Fifteen years ago, the novel concept of “Micro-View (on spots) ≈ Macro-View (on sites)” was first proposed by conceiving the transportation behavior of chemicals during spin cleaning (after L. Sheng et al., IRPS2006). Since that first success in promptly resolving a gate oxide integrity (GOI) crisis, we’ve been frequently searching for more instances of chemical and electrochemical kinetics being intricately tangled with wafer processing. As a result, we’ve gained broader insights by clarifying and resolving a range of intricate cases due to various defect generations.The gate oxide layer, often representing the smallest feature in modern metal-oxide-semiconductor (MOS) technologies, is critically susceptible to a variety of defectivity issues. Many steps in the frontend-of-line (FEOL) processing, especially at cleaning operations with various wet chemicals, deteriorate the conditions on wafer surface, which later incur defects inside the gate oxide layer as well as along its bottom and top interfaces. Furthermore, various corrosions have also been observed in the backend-of-line (BEOL) metallization, such as for the bimetallic AlCu bonding pads. Driven by the built-in potential differences across semiconductor devices, galvanism is also a common mechanism, which, however, has been far less recognized as in typical alloy materials.In this paper, the unique fundamentals of kinetic phenomena during semiconductor processing will be extensively reviewed for the first time. A comprehensive three-dimensional (3D) view provides the insights into chemical transportations along wafer surface and electrical cross-sections in device stack. In order to vividly illustrate the effectiveness of perceivably connecting these unique dynamics with critical defects generated, several case studies will be provided along complex process flows. Overall, these spatial revelations have made significant contributions to the solid technology development as well as the quality manufacturing of our most advanced high-voltage (HV) mixed-signal integrated circuit (IC) processes and products.

Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process

In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.

CMOS Compatible Atomic-Precision Donor Devices

Atomic precision advanced manufacturing (APAM) is a technique for placing dopant atoms with single atomic-lattice site precision on silicon surfaces. APAM devices are created by patterning the placement of dopants into a two-dimensional sheet of phosphorus atoms on the silicon surface, incorporating the dopants into the lattice, and then capping the device in silicon. The dopant atoms are incorporated into the silicon lattice through a surface-activated chemical reaction, as opposed to a thermally activated bulk process, which allows for electrically active doping above the solubility limit for phosphorus in silicon. The two-order of magnitude higher doping levels and two-dimensional nature of the dopant sheet enable new device physics and the potential for new device types with superior performance under specific tasks.Atomic precision fabrication requires atomically clean surfaces. Historically the APAM technique has required temperatures in excess of 1200 °C to prepare device surfaces, which has severely limited the ability to combine APAM with other manufacturing techniques such as CMOS. Recent work by our group and others has shown that the surface preparation process can be achieved at temperatures near 800 °C, greatly improving integration possibilities with CMOS [1,2]. Once fabricated, APAM devices have low thermal budgets to minimize vertical diffusion of the phosphorus dopants out of the non-equilibrium two-dimensional sheet. Temperatures on the order of 450 °C have been shown to be permissible for long periods of time.In this talk we report on the initial development of a CMOS process flow that incorporates APAM device fabrication. Based on the thermal budget and processing constraints, our basic process flow involves building the APAM device between CMOS Front-end-of-line (FEOL) and the CMOS Back-end-of-line (BEOL) steps. This is a natural insertion point based upon both thermal budget limitations and the need to directly access the device silicon to build the APAM device. Borrowing from CMOS nomenclature, we introduce the concept of “APAM select” and “APAM active” to indicate where the window for APAM device patterning will be opened and the actual APAM device area, respectively. These are the only additional mask layers needed to introduce APAM into a CMOS layout cell. An APAM cell was created that has the appropriate source/drain placement and targeting reticle in poly-Si to enable alignment of the APAM lithography tool to the wafer.Two classes of challenges exist in developing a CMOS-APAM process flow. The first is related to the APAM process itself and limitations of current fabrication tools. The APAM surface preparation, patterning, dopant incorporation, and silicon capping all occur in a scanning tunneling microscope (STM). Devices must be processed at the die level to fit into the STM sample holders. Die level processing puts restrictions on the BEOL processing including minimum feature size and available processes, such as a lack of chemical-mechanical polish (CMP) to planarize metal layers. The second class of challenges is related to the impacts of the APAM process, such as surface preparation, on CMOS devices, which has not been previously explored. We discuss our strategy for integration with CMOS, by including test structures to mimic the APAM device, and sequential implementation and testing of the APAM fabrication steps with CMOS chips.We conclude with a discussion of future integration challenges such as wafer level processing of APAM devices in a CMOS foundry flow. Direct integration of APAM components into CMOS circuits opens the door for devices with enhanced functionality.ACKNOWLEDGMENTThis work is supported by Sandia’s Lab Directed Research and Development Program, and was performed in part at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme---full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-of-line (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement- and routing-centric proximity attacks; correct connections are reduced by 7.47X, and complexity is increased by 24.15X, respectively, for such attacks.