Abstract
This work addresses the need for a comprehensive methodology for nanoscale electrical testing dedicated to the analysis of both “front end of line” (FEOL) (doped semiconducting layers) and “back end of line” (BEOL) layers (metallization, trench dielectric, and isolation) of highly integrated microelectronic devices. Based on atomic force microscopy, an electromagnetically shielded and electrically conductive tip is used in scanning microwave impedance microscopy (sMIM). sMIM allows for the characterization of the local electrical properties through the analysis of the microwave impedance of the metal–insulator–semiconductor nanocapacitor (nano-MIS capacitor) that is formed by tip and sample. A highly integrated monolithic silicon PIN diode with a 3D architecture is analysed. sMIM measurements of the different layers of the PIN diode are presented and discussed in terms of detection mechanism, sensitivity, and precision. In the second part, supported by analytic calculations of the equivalent nano-MIS capacitor, a new multidimensional approach, including a complete parametric investigation, is performed with a dynamic spectroscopy method. The results emphasize the strong impact, in terms of distinction and location, of the applied bias on the local sMIM measurements for both FEOL and BEOL layers.
Highlights
In “front end of line” (FEOL) processing, the control, detection, and quantification of the effective 2D distributions of active dopants in semiconductors are crucial to optimize and increase the device integration
In order to map the electrical properties of microelectronic materials with a high spatial resolution, scanning probe microscopy (SPM), based on atomic force microsco
Scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM) [3,4,5] are modes widely used for the detection of charge carriers, carrier types, and density of defects
Summary
In “front end of line” (FEOL) processing, the control, detection, and quantification of the effective 2D distributions of active dopants in semiconductors are crucial to optimize and increase the device integration. These modes provide sub-10 nm two-dimensional maps of the electrical properties of doped semiconductor layers [1,6,7,8] when a fixed bias is applied to the nanoscale contact.
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