Abstract
The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry.
Highlights
Accepted: 4 December 2020The 0.25 μm front-end-of line (FEOL) technology node was the first to replace the LOCOS integration scheme with shallow trench isolation (STI)
The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies
The continuous scaling needed for higher density and better performance has introduced new coverage challenges reviewed in this paper
Summary
The 0.25 μm FEOL (front end of line) technology node was the first to replace the LOCOS (local oxidation; see, e.g., [1]) integration scheme with shallow trench isolation (STI). The three main reasons for that were as follows: Published: 31 December 2020. Publisher’s Note: MDPI stays neutral with regard to jurisdictional clai-. Ms in published maps and institutional affiliations. Due to the formation of the bird’s beak, the conventional LOCOS isolation structure does not scale well. Limited depth of focus (DOF) for the gate patterning, due to the relatively large step height of the field oxide above the active area (AA) surface (Figure 1a). Stresses from the nitride layer over the pad oxide induced dislocations into the silicon and led to junction leakage
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