fractional-N Phase-locked Loop Research Articles

Fully integrated fractional‐N phase‐locked loop for GNSS standards

This study presents the design of a fully integrated fractional-N phase-locked loop (FNPLL) for the Global Navigation Satellite System (GNSS) applications. A new linearisation technique is presented for a charge pump (CP) circuit to improve the mismatch between the charging and discharging currents. The linearised currents help to reduce the static phase offset and the reference spurs of the FNPLL and the constant current helps to control the PLL dynamics precisely. The presented FNPLL is designed in a 0.18 µm CMOS technology. The simulation result reveals that the linearity of the CP is enhanced greatly when the technique is enabled and the current mismatch is <0.2 µA over the output voltage ranging from 0.2 to 1.65 V. The phase noise of the FNPLL at 10 and 100 KHz offset frequencies without the linearised CP are −85 and −90 dBc/Hz, respectively, and with the high linear CP are −90 and −97 dBc/Hz, respectively. The output power spectral density of the FNPLL shows that the power of the highest fractional spur is about −57 dBc. The lock time and the power consumption of the designed FNPLL are 50 µs and 11 mW from a 1.8 V power supply, respectively.

ΔΣ Fractional-N PLL With Hybrid IIR Noise Filtering

This brief presents a noise filtering method for wideband $\Delta \Sigma $ fractional-N phase-locked loop (PLL). The proposed hybrid infinite impulse response (IIR) phase noise filtering method reduces the building blocks compared to that of hybrid finite impulse response (FIR) filtering technique. A prototype 2-GHz $\Delta \Sigma $ fractional-N PLL with 1-MHz loop bandwidth is implemented in 130-nm CMOS process. Measurement results show that the proposed IIR filtering technique can suppress 5 dB more phase noise than the same order of FIR filter.

Multiplexed Twin PLLs for Wide-Band FMCW Chirp Generation in 130-nm BiCMOS

We present a pair of fractional-N phase-locked loops (PLLs) followed by a multiplexer (MUX) integrated in one chip. The PLL outputs are multiplexed during chirp generation to increase the frequency modulated continuous wave (FMCW) signal bandwidth to 5GHz around a 31-GHz center frequency. The phase noise measured at the MUX output is −108dBc/Hz at 1-MHz offset from a 31.07-GHz carrier. The chip occupies an area of 1.8 $\times $ 2.1mm2. The two PLLs together [excluding the voltage-controlled oscillators (VCOs)] draw 90mA from a 3.3-V supply, while the two VCOs, the MUX, and the output buffers draw 118mA from 2.7V. This array of PLLs offers a solution to improve resolution and precision of FMCW radar systems.

A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS

This letter presents a 12-GHz wideband fractional-N phase-locked loop (PLL) with a robust voltage-controlled oscillator (VCO). The proposed PLL uses a class-C VCO with an amplitude-adjustment circuit (AAC) to increase current during the startup process and stabilize the VCO amplitude. In order to make the circuit more compact, the control logic in the VCO is simplified. A prototype of the PLL implemented in 65-nm CMOS, with an active area of 1.5 mm2, can achieve −106 dBc/Hz phase noise (PN) at 1-MHz offset from a 11.96-GHz carrier. It draws 18.2-mW power with 48-MHz reference frequency from a 1.2-V supply.

A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation

This paper presents the theoretical and experimental results on the phase noise spectrum and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency-modulated continuous-wave (FMCW) chirp generation. The phase noise spectrum under modulation is analytically calculated for a second-order charge pump PLL with a feedback divider ratio linearly changing over time. This is followed by an analysis of the steady-state rms frequency error of the output frequency after PLL settling is achieved during chirp generation. A fractional-N PLL with integrated frequency ramp generator is presented. Phase noise and jitter measurements on the PLL under modulation are performed at the output of the programmable feedback divider. The resulting low-frequency rms jitter is reduced by about 9dB with doubling the charge pump current, and reduced by about 6dB with halving the ramp slope. The rms frequency error under FMCW modulation is measured at the modulated voltage-controlled oscillator output. The dependence of the frequency error on the loop filter capacitance for various ramp slopes is given. A frequency error of 112kHz is achieved with a ramp slope of 1.28GHz/80 μs at a carrier frequency of 62GHz. The noise measurements are in good agreement with the developed phase noise model. A programmable loop filter capacitance is suggested to accommodate the static phase offset and the resulting noise performance to the ramp slope.

Transmitters and receivers in SiGe BiCMOS technology for sensitive gas spectroscopy at 222 - 270 GHz

This paper presents transmitter and receiver components for a gas spectroscopy system. The components are fabricated in IHP’s 0.13 μm SiGe BiCMOS technology. Two fractional-N phase-locked loops are used to generate dedicated frequency ramps for the transmitter and receiver and frequency shift keying for the transmitter. The signal-to-noise ratio (SNR) for the absorption line of gaseous methanol (CH3OH) at 247.6 GHz is used as measure for the performance of the system. The implemented mixer-first receiver allows a high performance of the system due to its linearity up to an input power of -10 dBm. Using a transmitter-array with an output power of 7 dBm an SNR of 4660 (integration time of 2 ms for each data point) was obtained for the 247.6 GHz absorption line of CH3OH at 5 Pa. We have extended our single frequency-band system for 228 – 252 GHz to a 2-band system to cover the range 222 – 270 GHz by combining corresponding two transmitters and receivers with the frequency bands 222 – 256 GHz and 250 – 270 GHz on single transmitter- and receiver-chips. This 2-band operation allows a parallel spectra acquisition and therefore a high flexibility of data acquisition for the two frequency-bands. The 50 GHz bandwidth allows for highly specific and selective gas sensing.

A Novel Sensorless Rotor Position Detection Method for High-Speed Surface PM Motors in a Wide Speed Range

In order to improve the performance of surface permanent magnet synchronous motor drives, a novel sensorless drive scheme is proposed in this paper, which is based on the virtual third-harmonic back EMF incorporating a fractional-N phase-locked loop (FN-PLL) and a synchronous frequency-extract filter (SFF). A simple low-pass filter based circuit is used to obtain the commutation points through the virtual third-harmonic back EMF. After that, an FN-PLL is applied to obtain continuous rotor position angles. On this basis, the SFF-based compensation is proposed to compensate the detecting error adaptively. Meanwhile, the field vector control loop for surface PM motor is proposed, which is based on the proposed rotor position detection link and compensation link. An experimental high-speed magnetically suspended blower platform is built. The effectiveness and the feasibility of the proposed method are validated with experimental results.

Low-Noise Fractional-N PLL With a High-Precision Phase Control in the Phase Synchronization of Multichips

This letter presents a low noise fractional-N phase-locked loop (PLL) with a high-precision phase control. The resistors in loop filter and the current in the charge pump can be adjusted to achieve a reconfigurable loop bandwidth. A method to adjust the phase of the fractional-N PLL with high precision is proposed, which can be applied in the phase synchronization of multichips. The function of a high-accuracy phase control is added to the proposed sigma-delta modulator without adjusting the frequency division ratio. The prototype chip was fabricated using a 0.18- $\mu \text{m}$ CMOS process with an active area of 1.8 mm2. With a 1.8-V power supply, a reference frequency of 19.2 MHz, and a 2-GHz output radio frequency clock, this prototype achieves phase noise −122 dBc/Hz at 1 MHz while drawing 11.3 mW.

A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24–30-GHz Sliding-IF 5G Transceivers

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning of the voltage-controlled oscillator (VCO). The chip area of each PLL is 0.11 mm2, and 0.029 mm2 for the XO. The total power consumption of the system is 35 mW, where each PLL consumes 15.4 mW and the XO consumes 0.84 mW. The total rms jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just 115 fs, corresponding to an FOM $_{\vphantom {R_{j}}j}$ of −244 dB, which is the best reported figure for a fractional-N PLL above 15 GHz. The error-vector magnitude (EVM) due to phase noise is −34.6 dBc using an orthogonal frequency-division multiplexing (OFDM) signal with 120-kHz sub-carrier spacing, sufficient to support 256 QAM.

Design of Dual-Mode Local Oscillators Using CMOS Technology for Motion Detection Sensors

Recently, studies have been actively carried out to implement motion detecting sensors by applying radar techniques. Doppler radar or frequency-modulated continuous wave (FMCW) radar are mainly used, but each type has drawbacks. In Doppler radar, no signal is detected when the movement is stopped. Also, FMCW radar cannot function when the detection object is near the sensor. Therefore, by implementing a single continuous wave (CW) radar for operating in dual-mode, the disadvantages in each mode can be compensated for. In this paper, a dual mode local oscillator (LO) is proposed that makes a CW radar operate as a Doppler or FMCW radar. To make the dual-mode LO, a method that controls the division ratio of the phase locked loop (PLL) is used. To support both radar mode easily, the proposed LO is implemented by adding a frequency sweep generator (FSG) block to a fractional-N PLL. The operation mode of the LO is determined by according to whether this block is operating or not. Since most radar sensors are used in conjunction with microcontroller units (MCUs), the proposed architecture is capable of dual-mode operation by changing only the input control code. In addition, all components such as VCO, LDO, and loop filter are integrated into the chip, so complexity and interface issues can be solved when implementing radar sensors. Thus, the proposed dual-mode LO is suitable as a radar sensor.

470-MHz-698-MHz IEEE 802.15.4m Compliant RF CMOS Transceiver

This paper proposes an IEEE 802.15.4m compliant TV white-space orthogonal frequency-division multiplexing (TVWS)-(OFDM) radio frequency (RF) transceiver that can be adopted in advanced metering infrastructures, universal remote controllers, smart factories, consumer electronics, and other areas. The proposed TVWS-OFDM RF transceiver consists of a receiver, a transmitter, a 25% duty-cycle local oscillator generator, and a delta-sigma fractional-N phase-locked loop. In the TV band from 470 MHz to 698 MHz, the highly linear RF transmitter protects the occupied TV signals, and the high-Q filtering RF receiver is tolerable to in-band interferers as strong as −20 dBm at a 3-MHz offset. The proposed TVWS-OFDM RF transceiver is fabricated using a 0.13-μm CMOS process, and consumes 47 mA in the Tx mode and 35 mA in the Rx mode. The fabricated chip shows a Tx average power of 0 dBm with an error-vector-magnitude of < 3%, and a sensitivity level of −103 dBm with a packet-error-rate of < 3%. Using the implemented TVWS-OFDM modules, a public demonstration of electricity metering was successfully carried out.

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta–sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process, supply voltage, and temperature (PVT). The delta–sigma DAC with high power efficiency and linearity consists of a second-order delta–sigma modulator, a finite impulse response filter, and a low-pass filter. With the proposed PLL architecture, the frequency resolution can be lower than a few thousands of pulse per minute. The PLL is implemented in a 0.13- $\mu \text{m}$ 1P6M CMOS process. With temperature from −40 °C to 80 °C, the measured results of 15 chips show that the frequency deviation of output frequency in PVT decreases from 1 to 0.002 ppm. The phase noise of PLLs is less than −126 dBc/Hz at 1-MHz offset at a carrier frequency of 1.99 GHz. The rms period jitter is below 1 ps at 1.99 GHz, while consuming a total power of no more than 10 mW.

A novel zero dead zone PFD and efficient CP for PLL applications

This work presents a new structure of Phase Frequency Detector (PFD) and an improved design of Charge Pump (CP) for Phase Locked Loop applications. The new structure of PFD can overcome the speed and dead zone limitations of the conventional PFD. The interesting advantage of this PFD is that the reset path has been eliminated. Therefore, the blind zone is free and as a result the phase noise will be reduced. The proposed PFD has very simple structure with using only 8-transistor. Furthermore, the modified design of CP uses a new linearization technique to cancel the noise folding caused by interaction between CP and digital delta-sigma modulator. The proposed circuits are utilized in a fractional-N phase locked loop (FNPLL) for the 2.4 GHz IEEE 802.11 b/g is implemented in a 0.18 µm standard CMOS technology. The proposed FNPLL consumes 10.3 mW from a 1.8 V supply and have a phase noise of ź 86.18 and ź 90.4 dBc/Hz at 10 and 100 kHz frequency offsets, respectively.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

ABSTRACTA low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd‐order active‐RC filter is designed with current‐efficient feedforward compensated OTA. And a digital‐to‐time converter (DTC) assisted fractional‐N all‐digital phase‐locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. The presented receiver is fabricated in 55 nm CMOS technology with an active area of 2.3 mm2 and power consumption of 20 mW. Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out‐of‐band IIP3 is +8 dBm, and in‐band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in‐band PN and −120.5 dBc/Hz at 1 MHz offset.

A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a −78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 \times 4$ </tex-math></inline-formula> MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A fast-settling charge-pump PLL with constant loop bandwidth

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the $$\Delta \varSigma$$ modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump $$Icp$$ is programmed not only to compensate the variation of voltage-controlled oscillator gain $$Kvco$$ , but also for adapting to the change of divider ratio $$N_{m}$$ . This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is − 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized $$\left( {Icp*Kvco} \right)/N_{m}$$ which is equivalent to the variation of PLL loop bandwidth ranges from − 6 to 6%.

Resonance Frequency Readout Circuit for a 900 MHz SAW Device.

A monolithic resonance frequency readout circuit with high resolution and short measurement time is presented for a 900 MHz RF surface acoustic wave (SAW) sensor. The readout circuit is composed of a fractional-N phase-locked loop (PLL) as the stimulus source to the SAW device and a phase-based resonance frequency detecting circuit using successive approximation (SAR). A new resonance frequency searching strategy has been proposed based on the fact that the SAW device phase-frequency response crosses zero monotonically around the resonance frequency. A dedicated instant phase difference detecting circuit is adopted to facilitate the fast SAR operation for resonance frequency searching. The readout circuit has been implemented in 180 nm CMOS technology with a core area of 3.24 mm2. In the experiment, it works with a 900 MHz SAW resonator with a quality factor of Q = 130. Experimental results show that the readout circuit consumes 7 mW power from 1.6 V supply. The frequency resolution is 733 Hz, and the relative accuracy is 0.82 ppm, and it takes 0.48 ms to complete one measurement. Compared to the previous results in the literature, this work has achieved the shortest measurement time with a trade-off between measurement accuracy and measurement time.

Design and layout strategies for integrated frequency synthesizers with high spectral purity

Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.

Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL

A novel implementation technique for Vernier-based time-to-digital converters is reported. It is based on fractional-N phase-locked loops which allows the design of Vernier clocks with very close frequencies. The Vernier registers comparing counter values have been implemented in hardware in order to guarantee minimum detection latency of the moment of coincidence. Two Vernier clocks with close frequencies increment two 24-bit counters in a Cyclone V FPGA. A Vernier TDC with a demonstrated time resolution of 476ps is reported. It is also established that the time resolution limit that can be achieved with the suggested design is 10ps.