A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

Abstract

A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd‐order active‐RC filter is designed with current‐efficient feedforward compensated OTA. And a digital‐to‐time converter (DTC) assisted fractional‐N all‐digital phase‐locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. The presented receiver is fabricated in 55 nm CMOS technology with an active area of 2.3 mm2 and power consumption of 20 mW. Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out‐of‐band IIP3 is +8 dBm, and in‐band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in‐band PN and −120.5 dBc/Hz at 1 MHz offset.