Analysis of Time-to-Digital Converter to design a low power All Digital Phase Locked Loop

Abstract

A low power All Digital Phase Locked Loop (ADPLL) have become more attractive because they yield better testability, programmability, stability, and portability over different processes and the ADPLL has better noise immunity. All Digital Phase Locked Loop for digital system clock generation is widely studied to replace the traditional analog PLL. The goal of the Time-to-Digital Converter TDC is to measure the time difference between the rising edges of the signals. Time-to-Digital Converter (TDC) has been integrated in ADPLL to replace the analog charge pump. TDC with delay latch chain has been proposed to compare phase error between the reference clock and the feedback divided clock such design is for low power consumption. ADPLL designed via a vernier TDC with delay latch chain has been fabricated and the corresponding power consumed is 6.77 mW from a 1.8 V supply.