A 1.5GHz 0.2ps<inf>RMS</inf> jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS

Abstract

This paper presents a low power, low jitter, PVT-stable film-bulk acoustic wave resonator (FBAR) based all digital phase-locked loop (ADPLL) in a 65nm CMOS process. We introduce a power-efficient integer-N ADPLL architecture, where the digitally-controlled FBAR oscillator (FBAR DCO) achieves phase-lock to a reference clock without any explicit frequency dividers in the feedback path. The simplified divider-less ADPLL has a reduced phase difference at the input of the phase-frequency detector, avoiding a lengthy power hungry time-to-digital converter (TDC). The ADPLL consumes 1.5mW of power and has a measured integrated RMS jitter 0.19ps from 10kHz to 40MHz frequency offset at 1.5GHz carrier frequency. The measured frequency tuning range of 6300ppm for this ADPLL is wide enough to cover the FBAR frequency variations over PVT and provide moderate frequency modulation or channelization. This low power high performance FBAR ADPLL can be used in low power radios, high performance ADCs, and high speed data links.