Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

Abstract

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm2. The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.