A novel zero dead zone PFD and efficient CP for PLL applications

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This work presents a new structure of Phase Frequency Detector (PFD) and an improved design of Charge Pump (CP) for Phase Locked Loop applications. The new structure of PFD can overcome the speed and dead zone limitations of the conventional PFD. The interesting advantage of this PFD is that the reset path has been eliminated. Therefore, the blind zone is free and as a result the phase noise will be reduced. The proposed PFD has very simple structure with using only 8-transistor. Furthermore, the modified design of CP uses a new linearization technique to cancel the noise folding caused by interaction between CP and digital delta-sigma modulator. The proposed circuits are utilized in a fractional-N phase locked loop (FNPLL) for the 2.4 GHz IEEE 802.11 b/g is implemented in a 0.18 µm standard CMOS technology. The proposed FNPLL consumes 10.3 mW from a 1.8 V supply and have a phase noise of ź 86.18 and ź 90.4 dBc/Hz at 10 and 100 kHz frequency offsets, respectively.