fractional-N Phase-locked Loop Research Articles

A Compact, Low-Power, and Low-Jitter Fractional-N Phase-Locked Loop with a Single-Ended Ring Voltage-Controlled Oscillator in a 12 nm CMOS FinFET

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm2 area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range.

A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators

This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8.9-GHz output. By using the retiming and separate division techniques, frequency coupling is solved, and the implementation of the clock distribution is separated from its noise considerations, which alleviates design complexity. Fabricated in 65-nm CMOS process, the proposed CPPLL is verified, and it achieves −109.9-dBc/Hz@1 MHz phase noise and −71.6-dBc reference spur at 16-GHz output. The integrated jitter is 144 fs from 10 kHz to 100 MHz.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation

Fractional-N phase-locked loops using Harmonic-Mixer (HM) based feedback offer good phase noise and spur performance without relying on complex calibration schemes. The HMs in prior art are often realized using the Sample-and-Hold (S/H) operation. This, however, can result in unwanted tones due to intermodulation, which must be suppressed using properly-designed filters. This paper proposes a simple and accurate analysis of the location and magnitude of these tones. We also provide a design guideline for the HM based on this analysis to properly suppress these tones. The results are supported through behavioral and transistor-level simulations.

A Startup Control Method for Plasma Lamps by Using Fractional-N Phase-Locked Loop Microwave Driver

The microwave-driven plasma light source has the feature of the full spectrum, similar to sunlight, and has broad application prospects. Startups of plasma lamps are very difficult since the plasma density and the resonator impedance are changing constantly with the warm-up process and the RF driver can hardly couple the power to the plasma efficiently. This paper presents a startup control method for plasma lamps by using an integrated fractional-N phase-locked loop (PLL) as the RF signal source. An RF control module including a 21 dBm RF source with a band of 430–460 MHz and detection circuits for the RF driver is developed, and the startup process of the plasma lamp is further studied by analyzing the return loss of the resonator under the plasma load. According to the test result, the maximum frequency deviation of the RF control module is 3.3 kHz over the working temperature range of −40–80 °C. The designed RF control module is used to drive a high-power amplifier to start the plasma lamp automatically. It takes 79 s to achieve the stable arc operation from the gas breakdown. The return loss of the resonator is −26 dB, with an incident power of 171 W and reflected power of 418 mW, indicating that the RF driver and the plasma achieve good coupling. Compared with continuous wave, the luminous flux of the lamp powered by RF pulse improves by 18% under the same electric power. This startup control method has stable performance, small temperature drift, and an effective control function for plasma lamps.

A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications

ABSTRACT A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to . The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than – 12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies.

A method to shorten the frequency hopping time of fractional-N phase-locked loop

A method to shorten the frequency hopping time of fractional-N phase-locked loop

A 0.023–12 GHz ultra-wideband frequency synthesizer with FOMT of −251.8 dB

A fully integrated ultra-wideband fractional-N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional-N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional-N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOMT of −251.8 dB.

Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results.

A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer

A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW.

A K-Band FMCW Frequency Synthesizer Using Q-Boosted Switched Inductor VCO in SiGe BiCMOS for 77 GHz Radar Applications

In this article, a fractional-N phase-locked loop (PLL) with integrated chirp generation circuit block for a 76~81 GHz frequency-modulated continuous-wave (FMCW) radar system is presented. Thanks to the switched inductor voltage-controlled oscillator (VCO) topology, the linearity, phase noise, chirp bandwidth, and chirp rate of the FMCW synthesizer can be optimized for the short-range radar (SRR) and long-range radar (LRR) applications, with switch at ON/OFF states, respectively, according to different requirements and concerns. In this way, the proposed FMCW synthesizer shows improved phase noise for switch OFF-state, good for LRR applications, compared to the conventional single-varactor VCOs or cap-bank VCOs. The switch loss at ON-state is further decreased with the Q-boosting technique, which helps the FMCW synthesizer to simultaneously obtain a wide chirp bandwidth, steep modulation rates and good phase noise for SRR applications. The FMCW synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 1.7 × 1.9 mm2, and consumes 330 mW from a 3.3 V voltage supply. Measured results show that the FMCW synthesizer can cover 25.3~27 GHz (with a frequency tripler to fully cover 76~81 GHz band), showing optimized phase noise, chirp bandwidth, linearity, and modulation rates performance. The measured K-band phase noise is −110.5 dBc/Hz for switch OFF-state, and −106 dBc/Hz for switch ON-state at 1 MHz offset. The normalized root mean square (RMS) frequency error is 518 kHz for chirp rate of ±14.6 MHz/μs and 1.44 MHz for chirp rate of ±39 MHz/μs for the 77 GHz band. Moreover, the integrated waveform generator offers fully programmability in chirp rate, duration and bandwidth, which supports multi-slope chirp generations. With a frequency tripler, the chip is well suited for the 76~81 GHz FMCW radar system.

Suppression of Spur Chirps for Fractional-N PLL-Based Heterodyne FMCW SAR

Fractional-N phase-locked loops (PLLs) offer a low-cost solution to the precision frequency ramp requirements of frequency-modulated continuous-wave (FMCW) radar. Regrettably, however, these PLLs are known to produce undesirable spurii in their synthesized output. A subset of these spurii has recently been shown to manifest as frequency chirps, also known as spur chirps , in the deramped beat signal. These so-called spur chirps give rise to Fresnel ripples in the range domain after standard Fourier processing. Spur chirps are of particular concern for heterodyne receiver systems because the Fresnel ripples may appear at levels that far exceed the noise floor. In this article, the authors present guidelines for the avoidance of spur chirps and identify existing interference suppression techniques that are transferable to this problem. Furthermore, the authors put forward a novel technique termed range-Doppler spur masking (RDSM) that was designed specifically for the suppression of spur chirps. The developed technique was applied to both the simulated and measured synthetic aperture radar (SAR) data. Simulations reveal that RDSM significantly outperforms time-domain zeroing in terms of peak sidelobe ratio (PSLR) and other metrics. When applied to the measured data, RDSM is shown to eliminate the effects of the spur chirps in SAR imagery when masking only 0.15% of the available Doppler bins.

Phase Coherent Frequency Hopping in Direct Digital Synthesizers and Phase Locked Loops

Phase coherent, frequency hopping direct digital synthesizer (DDS) and Type-II phase locked loop (PLL) circuits are presented in this paper. The proposed approach eliminates the memory effects of prior frequency states in the phase (DDS) and fractional (PLL) accumulators by employing a master accumulator with a fixed increment and multiplying its output to generate the appropriate phase and fractional outputs. This approach allows for an arbitrary sequence of frequency hops, since it is not based on multiple simultaneous accumulators to store phase. We present phase coherent topologies for standard and parallelized DDS circuits, a fractional-N PLL and a multistage sigma-delta modulator (MASH)-111 fractional-N PLL, along with mathematical analysis showing phase coherency. We also present measured results of parallelized DDS and MASH-111 fractional-N PLL hardware.

Current pulse shaping technique for low spur fractional‐N phase‐locked loop

Current pulse shaping technique is proposed for low spur fractional-N phase-locked loop, which is realised by a variable amplitude charge pump (VA-CP) and a fixed-position, fixed-width and variable-period pulse generator (FFVPG). The current pulse of VA-CP driven by the FFVPG is shaped to fixed position, fixed width, variable amplitude and variable period for eradicating both reference spurs and fractional spurs. The period of VA-CP's current pulse is T REF during transient and N 1 × T REF during locking status, in which the N 1 should be properly set in order to reduce fractional spurs as far as possible and accelerate locking time. The spur performance of the proposed fractional phase-locked loop is evaluated by analysing the spectrum of tuning voltage when reference frequency is 20 MHz and division ratio is 120.13. Spectre based simulation results show the reference spurs at integer multiplies of 20 MHz is eradicated, and the fractional spurs at 10 MHz and the other fractional frequencies are 19.67 dB and much less than that with the existing technique, which verify the feasibility of this study.

Fully Integrated Dual-Mode X-Band Radar Transceiver Using Configurable Receiver and Local Oscillator

In this paper, a fully-integrated dual-mode X-band radar transceiver that supports Doppler radar and frequency modulated continuous wave (FMCW) radar is proposed. To remove large off-chip DC-blocking capacitors in the Doppler mode, the double-conversion technique and local oscillator (LO) chopping technique are introduced. These techniques remove the DC offset and makes the transceiver more robust to the TX to RX leakage. In addition, they also improve the noise figure (NF) by filtering out 1/f noise of the analog baseband. The FMCW radar is realized using a direct-conversion receiver and a chirp generator. The chirp generator consists of a frequency sweep generator (FSG) and a fractional-N phase-locked loop (PLL). All the analog baseband components including a programable gain amplifiers (PGA) and 1/R 4 range compensation filters are integrated on the chip as well as a bandgap and low-dropout regulators. The operating frequency is from 9.7 to 12.3 GHz, which consumes 216 mW in Doppler mode and 201.6 mW in FMCW mode from a 1.2-V supply voltage. The maximum chirp bandwidth is 750 MHz and the maximum receiver gain is 76 dB with 6-dB gain step. The chip size of the transceiver is 7.68 mm 2 including all the pads.

A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS

A fully synthesizable injection-locked phase-locked loop (IL-PLL) for digital clocking is proposed in this letter. The phase-locked loop (PLL) is implemented in a 5-nm CMOS process, with only digital standard cells are used. With proposed triple-path operation and digital offset control for digital-to-time converter (DTC), low-jitter fractional-N frequency synthesis, and highly-linear spread-spectrum clocking are realized with low-power consumption. The PLL core area is 0.0036 mm2. With 100-MHz reference frequency, better than −234.7 dB figure-of-merit (FOM) is achieved in the fractional-N mode, with −44.3 dBc worst-case fractional spur. The proposed PLL has the smallest chip area, highest FOM, and lowest fractional spur among ring oscillator (RO)-based fractional-N PLLs in sub-20-nm processes.

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

A fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4th- and 5th-order single-loop (SL) and 3rd- and 4th-order multi-stage noise-shaping (MASH) ones. SL-DSMs with fewer output levels resulting in smaller instantaneous phase error, achieve better phase noise. MASH DSMs with wider quantization levels having more efficient randomization and dithering effects, generate less fractional spur. Experimental results show that in-band and out-of-band fractional spurs of MASH DSM are 10.5 and 5.8dB better than those of SL-DSM, respectively, while out-of-band phase noise of SL-DSM is 4.5dB lower than that of MASH DSM, with the same order. The fractional-N PLL is fabricated in 180nm CMOS with a 1.8V supply voltage and power consumption of approximately 23mW.

A Scalable 79-GHz Radar Platform Based on Single-Channel Transceivers

This paper presents a scalable E-band radar platform based on single-channel fully integrated transceivers (TRX) manufactured using 130-nm silicon–germanium (SiGe) BiCMOS technology. The TRX is suitable for flexible radar systems exploiting massive multiple-input-multiple-output (MIMO) techniques for multidimensional sensing. A fully integrated fractional-N phase-locked loop (PLL) comprising a 39.5-GHz voltage-controlled oscillator is used to generate wideband frequency-modulated continuous-wave (FMCW) chirp for E-band radar front ends. The TRX is equipped with a vector modulator (VM) for high-speed carrier modulation and beam-forming techniques. A single TRX achieves 19.2-dBm maximum output power and 27.5-dB total conversion gain with input-referred 1-dB compression point of −10 dBm. It consumes 220 mA from 3.3-V supply and occupies $3.96~\mathrm {mm^{2}}$ silicon area. A two-channel radar platform based on full-custom TRXs and PLL was fabricated to demonstrate high-precision and high-resolution FMCW sensing. The radar enables up to 10-GHz frequency ramp generation in 74–84-GHz range, which results in 1.5-cm spatial resolution. Due to high output power, thus high signal-to-noise ratio (SNR), a ranging precision of 7.5 $\mu \text{m}$ for a target at 2 m was achieved. The proposed architecture supports scalable multichannel applications for automotive FMCW using a single local oscillator (LO).