A fast-settling charge-pump PLL with constant loop bandwidth

Abstract

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the $$\Delta \varSigma$$ modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump $$Icp$$ is programmed not only to compensate the variation of voltage-controlled oscillator gain $$Kvco$$ , but also for adapting to the change of divider ratio $$N_{m}$$ . This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is − 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized $$\left( {Icp*Kvco} \right)/N_{m}$$ which is equivalent to the variation of PLL loop bandwidth ranges from − 6 to 6%.