Low-Noise Fractional-N PLL With a High-Precision Phase Control in the Phase Synchronization of Multichips

Abstract

This letter presents a low noise fractional-N phase-locked loop (PLL) with a high-precision phase control. The resistors in loop filter and the current in the charge pump can be adjusted to achieve a reconfigurable loop bandwidth. A method to adjust the phase of the fractional-N PLL with high precision is proposed, which can be applied in the phase synchronization of multichips. The function of a high-accuracy phase control is added to the proposed sigma-delta modulator without adjusting the frequency division ratio. The prototype chip was fabricated using a 0.18- $\mu \text{m}$ CMOS process with an active area of 1.8 mm2. With a 1.8-V power supply, a reference frequency of 19.2 MHz, and a 2-GHz output radio frequency clock, this prototype achieves phase noise −122 dBc/Hz at 1 MHz while drawing 11.3 mW.