For Fully Depleted Silicon-on-insulator Research Articles

Gate-controlled gain tuning of fully depleted silicon-on-insulator-based 1 T pixel for in-sensor white balance

White balance (WB) is a critical back-end processing function in image sensors to keep color constancy under various lighting conditions by adjusting the RGB color channel gain values. In this work, we proposed a novel gate-controlled gain-tuning method for a fully depleted silicon-on-insulator (FDSOI) one-transistor (1 T) pixel to achieve WB inside the sensor. Based on the pixel structure of a p-well under the buried oxide for sensing and an n-type nMOSFET on the top for readout, the 1 T pixel output gain is modulated by the MOSFET gate according to the transistor transfer characteristics. About 5x gain modulation range in RGB spectrum photoresponse (nonlinearity < 3%) is experimentally demonstrated in the devices fabricated by 22 nm FDSOI-based technology. The scheme for in-sensor WB demonstration is provided with a novel 1 T pixel array design, and the evaluation result shows in-sensor WB achieving an almost equivalent performance (Delta-E deviation < 1) compared with using conventional back-end WB.

Material level analytical model of total ionizing dose induced DC characteristics shift for FDSOI IC design

A charge build-up model implemented in a netlist coupled with L-UTSOI model, which takes into account the deposited dose as an input parameter, is presented for Fully Depleted Silicon On Insulator (FDSOI) transistors. The model is based on the rate equations governing the physical processes of the charge build-up in the oxides. Based on in-house irradiation measurement, our model is calibrated on experimental Id-Vg characteristics in order to find the model parameters and extract the contribution of the oxide and interface trapped charges.

Total-Ionizing-Dose Effects on 3-D Sequentially Integrated FDSOI Ring Oscillators

Total-ionizing-dose responses are investigated for fully-depleted silicon-on-insulator (FDSOI) ring oscillators (RO), in three-dimensional (3D) architectures. Operational frequencies decrease after irradiation in these devices due primarily to threshold voltage shifts and transconductance degradation due to interface-trap buildup in the pull-up <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> MOSFETs. 3D sequentially-integrated FDSOI ROs fabricated in the bottom layer of the 3D structure show the most significant frequency degradation. AC-bias irradiation leads to greater shifts than static-bias irradiation in these devices due to enhanced interface-trap buildup. Circuit simulations reinforce the relative importance of transconductance degradation in pull-up <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> MOSFETs to the TID response of these ROs.

Prediction of Single-Event Effects in FDSOI Devices Based on Deep Learning

Single-event effects (SEE) are an important index of radiation resistance for fully depleted silicon on insulator (FDSOI) devices. The research into traditional FDSOI devices is based on simulation software, which is time consuming, requires a large amount of calculation, and has complex operations. In this paper, a prediction method for the SEE of FDSOI devices based on deep learning is proposed. The characterization parameters of SEE can be obtained quickly and accurately by inputting different particle incident conditions. The goodness of fit of the network curve for predicting drain transient current pulses can reach 0.996, and the accuracy of predicting the peak value of drain transient current and total collected charge can reach 94.00% and 96.95%, respectively. Compared with TCAD Sentaurus software, the simulation speed is increased by 5.10 × 102 and 1.38 × 103 times, respectively. This method can significantly reduce the computational cost, improve the simulation speed, and provide a new feasible method for the study of the single-event effect in FDSOI devices.

A Computationally Efficient Model for FDSOI MOSFETs and Its Application for Delay Variability Analysis

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8× and 1.4× acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21× reduction in computational time.

Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology

The electrostatic discharge (ESD) protection is always a challenge for fully depleted silicon on insulator (FD-SOI) CMOS technology. Today, several efficient and robust solutions are available. In the framework of optimized solutions, it is interesting to investigate a protection according to its topology and design. First of all, this study will be based on 3D TCAD analysis of thin silicon film Bipolar MOS (BIMOS) devices with standard topology and with optimized body access. Then the design will be modified by adding new devices or by adjusting the parasitic elements. The aim is to better understand the device behavior and to push the performance. Additionally, silicon demonstrators have been fabricated, characterized and investigated. It appears that each design has advantages and drawbacks and should be chosen in accordance with the final implementation. The proposed design can also be ported to another technology node with an adaptation.

Closed-Form Analysis of Metastability Voltage in 28-nm UTBB FD-SOI CMOS Technology

In this brief, analytical expressions for the metastability voltage of latch-type comparators at sub-threshold operation are advanced. Drain induced barrier lowering (DIBL) and body bias effects are investigated in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Since, metastability voltage variations have been widely studied as the major cause of latch input offset, statistical expressions are also derived to estimate the yield of latch-type comparators. The analytical results show close agreement with extensive HSPICE simulations using a 28-nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.

Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology

In this paper, analytical expressions for the conventional definition of write static noise margin (WSNM) for 6T-SRAM cells at sub-threshold operation are derived. Drain-induced barrier lowering (DIBL) and body-biasing effects are considered in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. By observing the expressions for WSNM and read SNM (RSNM) we introduce an alternative design parameter (Γ) for 6T-SRAM cell sizing, whose purpose is to control read and write static noise margins simultaneously, thereby providing effective stability balance. This paper also shows that low-leakage cells with suitable stability can be designed by using a non-traditional sizing for 6T-SRAM cells, in which increased transistor lengths are employed to reduce leakage, assisted by a word-line voltage reduction technique to increase read margin. In addition, a statistical analysis for both read and write static noise margins taking into account manufacturing process variations was carried out with the purpose of designing a high-yield 6T cell. Analytical expressions and the designed 6T cell were verified by extensive HSPICE simulations using a 28 nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

No models exist for fully depleted silicon‐on‐insulator (FD‐SOI) metal‐oxide‐silicon field‐effect‐transistors (MOSFETs) that operate at high currents and voltages. Operation at high currents and voltages dictates the radio‐frequency (rf) output power that such devices can deliver and transmit from the particular rf‐integrated circuits used in today's cellular phones. In this work, a first order dc model for FD‐SOI MOSFETs that are specifically designated to operate at high biases and large rf swings is presented. These devices typically incorporate HALO and body‐tied‐source (BTS), which enable much higher biases to be applied to the gate and drain and allow larger rf swings. They also employ dual‐gated designs that further reduce the threshold voltage and increase the current. Although the newly established model accurately replicates the general dc behavior of any FD‐SOI MOSFET that incorporates HALO and BTS, it is specifically tailored to an innovative and recently patented device structure for FD‐SOI MOSFET. The new structure adopts an improved and unique design for BTS and HALO that most effectively filters the impact‐ionization current to BTS and improves the device performance. New design rules that enable the designs of area‐efficient layouts for FD‐SOI MOSFETs that incorporate the HALO and BTS are also presented.

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.

Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs

An X-ray irradiation degradation mechanism has been investigated for fully depleted-silicon-on-insulator (FD-SOI) p-channel MOSFETs (p-MOSFETs). It is found that the drain current degradation by the X-ray irradiation has gate length dependence showing 20% degradation for $L=0.2\,\, \mu \text{m}$ , while 8% for $L=10\,\, \mu \text{m}$ after the 1.4 kGy(Si) X-ray irradiation. Using Terada’s method, it was found that the degradation is not due to mobility degradation but due to radiation-induced gate length modulation (RIGLEM) and the associated increase of source and drain parasitic resistance. The major cause of degradation induced by the RIGLEM is explained by an analytical model, assuming a positive charge generation in sidewall spacers. It can be suggested that the X-ray irradiation degradation of FD-SOI p-MOSFET can be improved by optimizing the lightly doped drain region.

The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator With Thin Box Layer MOSFETs

In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability.

Compact model of short-channel effects for FDSOI devices including the influence of back-bias and fringing fields for Si and III–V technology

In this work, a compact model for short-channel effects is proposed for fully depleted silicon-on-insulator (FDSOI) MOSFETs, which takes into account the impact of body-bias and fringing fields, developed to be suitable for both thin and thick buried oxide (BOX) devices. The model is derived using the Voltage-Doping Transform, confirmed with TCAD simulations and experimental data from the literature. The impact of the BOX thickness on the subthreshold swing and the contribution of the leakiest path position to the DIBL are finally discussed.

Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10 nm node

This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs

In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator (FDSOI) devices fabricated with a low thermal budget (⩽650°C), which commonly exhibit leakage problems due to the presence of defects in or close to depletion regions. We show through both experimental data and Kinetic Monte Carlo (KMC) simulations that the reduction of the film thickness and Raised Source Drain (RSD) allow the elimination of defects in critical regions in spite of the reduced thermal budget in the very early stage of the anneal. KMC simulations also show that defects are annealed-out in this critical region even for 500°C anneals. Low temperature process appears then as a suitable process for advanced devices.

Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes

Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600–700 °C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850 °C for 20 s, by which subsequent source/drain activation can be carried out.

Accurate Small-Signal Modeling of FD-SOI MOSFETs

A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.

Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide

The short-channel threshold voltage model for fully depleted (FD) silicon-on-insulator (SOI) MOSFETs, based on a quasi-2D approach, has been investigated and extended. The effect of the source/drain fringing fields, which penetrate into the buried oxide, has been taken into account by using an extra 2D analytical equation which is based on conformal mapping. This equation models the enhanced short-channel behavior of the FD SOI MOSFET in the buried oxide. The extended quasi-2D analytical threshold voltage model has been compared to 2D Medici simulation data, down to channel lengths of 0.1 μm. The obtained results show good agreement between the analytical model and 2D Medici simulation data.