Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology

Abstract

In this paper, analytical expressions for the conventional definition of write static noise margin (WSNM) for 6T-SRAM cells at sub-threshold operation are derived. Drain-induced barrier lowering (DIBL) and body-biasing effects are considered in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. By observing the expressions for WSNM and read SNM (RSNM) we introduce an alternative design parameter (Γ) for 6T-SRAM cell sizing, whose purpose is to control read and write static noise margins simultaneously, thereby providing effective stability balance. This paper also shows that low-leakage cells with suitable stability can be designed by using a non-traditional sizing for 6T-SRAM cells, in which increased transistor lengths are employed to reduce leakage, assisted by a word-line voltage reduction technique to increase read margin. In addition, a statistical analysis for both read and write static noise margins taking into account manufacturing process variations was carried out with the purpose of designing a high-yield 6T cell. Analytical expressions and the designed 6T cell were verified by extensive HSPICE simulations using a 28 nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.