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Abstract
In this brief, analytical expressions for the metastability voltage of latch-type comparators at sub-threshold operation are advanced. Drain induced barrier lowering (DIBL) and body bias effects are investigated in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Since, metastability voltage variations have been widely studied as the major cause of latch input offset, statistical expressions are also derived to estimate the yield of latch-type comparators. The analytical results show close agreement with extensive HSPICE simulations using a 28-nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.
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