Abstract
The electrostatic discharge (ESD) protection is always a challenge for fully depleted silicon on insulator (FD-SOI) CMOS technology. Today, several efficient and robust solutions are available. In the framework of optimized solutions, it is interesting to investigate a protection according to its topology and design. First of all, this study will be based on 3D TCAD analysis of thin silicon film Bipolar MOS (BIMOS) devices with standard topology and with optimized body access. Then the design will be modified by adding new devices or by adjusting the parasitic elements. The aim is to better understand the device behavior and to push the performance. Additionally, silicon demonstrators have been fabricated, characterized and investigated. It appears that each design has advantages and drawbacks and should be chosen in accordance with the final implementation. The proposed design can also be ported to another technology node with an adaptation.
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