Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes

Abstract

Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600–700 °C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850 °C for 20 s, by which subsequent source/drain activation can be carried out.