Hot Carrier Effects Research Articles

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

Designing digital circuits using 3D nanomagnetic logic architectures

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.

Identification of Channel Hot Carrier Stress-Induced Oxide Traps Leading to Random Telegraph Signals in pMOSFETs

We investigated the effect of channel hot carrier (CHC) stressing on the creation of gate oxide defect centers causing random telegraph signals (RTSs) in pMOSFETs. To identify these stress-induced hole traps in the oxide and fully characterize their trapping properties, variable temperature RTS measurements were performed from room temperature down to 215 K and repeated after each stressing interval, up to 1200 s. The trapping properties of the stress-induced defect sites and those present before stress are quantified, including the hole capture and emission activation energies, structural relaxation in the oxide network due to trapping/detrapping, and entropy change as well as the energy level and position of the trap in the oxide. Based on this information, disassociated III-Si and hydrogen bridge defects are identified as the hole trapping centers in SiO2. Difference was observed between the process- and stress-induced traps in the entropy change upon hole emission from the oxide trap to Si channel (electron capture from the Si valence band), implying the possibility of stress-induced structural defects being different than the native ones.

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage ( V TH1 ) could be reduced compared to the external gate ( V TH2 ) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Hot Carrier Effect in Self-Aligned In–Ga–Zn–O Thin-Film Transistors With Short Channel Length

This study examines the impact of channel length ( $L$ ) on the performance of amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors with self-aligned structures. The negative threshold voltage ( ${V}_{\text{TH}}$ ) displacement for IGZO transistors with increasing drain voltage ( ${V}_{\text{DS}}$ ) becomes severe with decreasing ${L}$ from 10 to $2~ \mu \text{m}$ . The $V_{\text{DS}}$ -dependent negative $V_{\text{TH}}$ shift can be mitigated by increasing the oxygen flow rate (OFR) ratio during a-IGZO preparation from 40% to 80%, which suppresses the number of oxygen vacancy defects near the n+ drain of the a-IGZO region. In contrast, the hot carrier stress (HCS)-induced degradation in terms of the threshold voltage was accelerated for devices with increasing OFR ratio, presumably due to the creation of excessive oxygen-originated defects. The rationale for these observations is discussed with regard to the increasing local electric field near the drain junction, which was calculated by technology computer-aided design (TCAD) simulation. We concluded that an acceptable compromise between short channel effect and HCS-induced degradations can be achieved by choosing an intermediate OFR ratio of 64%.

Investigation of the spatial distribution of hot carriers in quantum-well structures via hyperspectral luminescence imaging

Observation of robust hot carrier effects in quantum-well structures has prompted hopes to increase the efficiency of solar cells beyond the Shockley–Queisser limit (33% for single junction solar cells at AM1.5G). One of the main studies in hot carrier effects is the determination of carrier temperature, which provides information on the thermalization mechanisms of hot carriers in semiconductor materials. Here, we investigate the spatial distribution of photo-generated hot carriers in a InGaAs multi-quantum-well structure via hyperspectral luminescence imaging. We discuss proper methods of extracting the temperature of carriers from a photoluminescence spectrum. Robust hot carrier effects are observed at the center of the laser spot at various lattice temperatures. In addition, it is seen that the local carrier temperature scales linearly with the local laser intensity as long as the illumination exceeds a threshold power; the carrier temperature at regions with local intensities below the threshold drops to the lattice temperature, i.e., experiences no hot carrier effects. Moreover, at large distances from the concentrated light, where the level of illumination is negligible, evidence of carrier radiative recombination is observed, which is attributed to carrier diffusion in the planar structure. The results of this study can be applied to investigate the influence of carrier diffusion and thermoelectric effects on the thermalization of hot carriers.

Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFET

This paper presents explicit analytical modeling of a gate all around (GAA) strained silicon metal-oxide-semicondutor field-effect transistor (MOSFET) with elliptical cross section by incorporating the popular gate work function engineering (WFE) concept of lateral mole fraction variation from source to drain end. Surface potential and threshold voltage formulation of the proposed structure based on a quasi-three-dimensional scaling equation have been introduced. The derived model is further used to investigate the short channel characteristics of the device in terms of hot carrier effect (HCE), drain-induced barrier lowering (DIBL), threshold voltage roll off (TVRO), and subthreshold slope. The impact of device parameter variation including gate oxide thickness, effective radius, channel doping concentration, germanium (Ge) mole fraction variation in the strained silicon channel along with applied gate to source and drain biases are evaluated on device performance to justify its efficiency in comparison to its single gate material (SM) MOSFET equivalent. Our analytical analysis is further validated by ATLAS-3D device simulated data to verify the precision of the derived model.

(Invited) Hot Carrier Phenomena in Oxide Thin-Film Transistors

Oxide thin-film transistors (TFTs) using amorphous oxide semiconductors such as a-InGaZnO4 (a-IGZO) are attracting attention for realizing next generation displays as well as for flexible mobile devices. From a point of practical use, it is important to achieve stable electrical characteristics in oxide TFTs. Thus various reports have been made on instability of oxide TFTs’ characteristics, such as threshold voltage shift and a light deterioration phenomenon caused by application of bias voltage or light illumination.1-3) Hot carrier effects, however, induced by high drain voltage in oxide TFTs have been still unclear.Hot carrier effects are well-known phenomena in low temperature polycrystalline Si TFTs, and photon emission has been observed under high drain voltage.4) In recent years, we also have observed photon emission under high drain voltage for etch stop layer (ESL)-type oxide TFTs with a source/drain (S/D) that overlapped less than 1 µm on ESL.5) In this paper, we discuss the hot carrier effects depends on structures of oxide TFTs.We fabricated back channel etching (BCE)-type, top gate (TG)-type and ESL-type5) TFTs using oxide semiconductor material as active layers as shown in Fig. 1(a), (c) and (e), respectively. For BCE-type TFTs, a gate, a gate insulator, a-IGZO, S/D and a passivation were formed on a glass substrate in that order. For TG-type TFTs, low resistance regions in amorphous oxide semiconductor layer, which has higher mobility than a-IGZO, were self-aligned to the gate. For the ESL-type TFTs, an overlap length of the S/D on the ESL was 3 µm. Other fabrication process were described in previous report.5-6) As shown in Fig. 1(b), for the BCE-type TFT with channel width (W) /channel length (L) =15 µm/8 µm under Vds=25 V and Vgs=10 V, photon emission was observed at the drain edge opposite to the source. Two positions where most photon was irradiated correspond to those where the drain slightly extends to the source. As shown in Fig. 1(d), for the TG-type TFT with W/L = 10 µm/10 µm under Vds=40 V and Vgs=18 V, photon emission was observed at the gate edge opposite to the drain and at the drain edge opposite to the gate. For both these two regions, positions where most photon was irradiated correspond to the edge of active layer, which is often pointed out as one of the causes of instability of TFT characteristics.6) Although drain current (Ids) increased at higher Vgs than Fig. 1(b) and (d), photon counts decreased. From these results, we consider the observed photon emission were induced by hot carrier in the oxide semiconductor layers and photon emission images show regions which may affect instability of TFT characteristics.On the other hands, for the ESL-type TFT with channel width (W) /channel length (L) =5 µm/14 µm, photon emission was not observed even under drain voltage (Vds) =40 V and gate voltage (Vgs) =12 V as shown in Fig. 1(e). However, we experimentally observed that when the overlap length of the drain on the ESL decreases from 3 µm to 0 µm, photon emission was observed. Furthermore, TCAD simulation showed that the large electric field of 3.5×105 V/cm appears locally at the drain edge for the overlap length=0 μm while that relaxed to less than 2.2×105 V/cm for the overlap length>1 μm. These results suggest that existence of the drain/ESL overlap region can weaken the electric filed at the drain edge, and as a result we do not see photon emission in the ESL-type TFT with the overlap length=3 µm.In summary, we evaluated hot carrier effect for the BCE-, the TG-type and the ESL-type oxide TFTs with photon emission analysis. Photon emission was observed for the BCE- and the TG-type TFT while it was not observed for the ESL-type TFT with the overlap length of the drain on the ESL=3 µm. We consider one of reasons of these results would be difference in the structure near the drain of each TFT. In the PRiME 2020 meeting, we would like to discuss these phenomenon in detail using experiment and TCAD simulation.References1) K. Takechi et al., Jpn. J. Appl. Phys., 48, 010203 (2009).2) J. Tanaka et al., ECS Journal of Solid State Science and Technology, 4 (7) Q61 (2015).3) Y. Uraoka et al., Jpn. J. Appl. Phys., 58, 090502 (2019).4) Y. Uraoka et al., IEEE Trans. Electron Devices, 51, 28 (2004).5) T. Takahashi et al., Appl. Phys. Express, 12, 094007 (2019).6) Y. Kuwahara et al., IEEE Electron Device Lett., 40, 8 (2019). Figure 1

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) devices are expected to face new challenges such as exponential current leakage, DIBL, hot carrier effects, and etc. at nano scale. Hence the CMOS technology is being supplanted by the nanotechnologies. Quantum-dot Cellular Automata (QCA) is key technology at nano scale which operates at tera hertz of speed. Comparing with the traditional CMOS technology, the QCA technology has low power consumption and high density. This technology also has a unique methodology such as “processing in wire” and “memory-in-motion”. This work confers an area proficient, high speed full adder (FA) design with efficient clocking. The proposed full adder design comprises of 26 Quantum cells with delay of two clock phases, area occupancy of 0.03 µm 2 . This paper utilizes the unique characteristics of QCA and the proposed Wallace tree multiplier is implemented with the mentioned FA and is designed by using QCA Designer 2.0.3 tool.

Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications

In this paper, we have investigated the performance of a silicon-based low-doped drain (LDD) SOI-FinFET for the first time and compared it with conventional FinFET for implementation in logic circuits. It is well known that the use of the conventional LDD technology in the triple gate FinFETs reduces the electric field near the drain region and hot carrier effect at the cost of reduced current driving capability as is reported in LDD MOSFETs. We observe a reduction in the peak electric field by 15% near the drain region with a subsequent degradation in the electron velocity, as well. We have presented a semi-analytical approach to model the gate capacitance, drain current, channel potential, and subthreshold slope for the proposed FinFET structure. 3D simulation results for three different channel lengths using the TCAD Sentaurus tool are used to validate the computed results. DC analysis of the LDD-FinFET is performed and results are compared with the conventional FinFET device in terms of threshold voltage, transconductance, and $$I_{\text {ON}}/I_{\text {OFF}}$$ ratio. The capacitance model is used to investigate the subthreshold swing and current driving capability of the proposed device. In addition to this, circuit-level analysis like voltage transfer characteristics and switching characteristic of proposed CMOS inverter using SOI LDD-FinFET is performed. The results presented in this paper can be utilized for the design of low-power digital applications to cater to the requirements of high switching speeds, high gain, and minimum power dissipation.

Enhancing Hot-Carrier Reliability of Dual-Gate Low-Temperature Polysilicon TFTs by Increasing Lightly Doped Drain Length

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative Vth shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.

Decelerated Hot Carrier Cooling in Graphene via Nondissipative Carrier Injection from MoS2.

One key to improve the performance of advanced optoelectronic devices and energy harvesting in graphene is to understand the predominant carrier scattering via optical phonons. Nevertheless, low light absorbance in graphene yields a limited photoexcited carrier density, hampering the hot carrier effect, which is strongly correlated to the hot optical phonon bottleneck effect as the energy-loss channel. Here, by integrating graphene with monolayer MoS2 possessing stronger light absorbance, we demonstrate an efficient interfacial hot carrier transfer between graphene and MoS2 in their heterostructure with a prolonged relaxation time using broadband transient differential transmittance spectroscopy. We observe that the carrier relaxation time of graphene in the heterostructure is 4 times slower than that of bare graphene. This is explained by nondissipative interlayer transfer from MoS2 to graphene, which is attributed to the enhanced hot optical phonon bottleneck effect of graphene in the heterostructure by an increased photoexcited carrier population. A significant reduction of both amplitude and relaxation time in A- and B-excitons is another evidence of the interlayer transfer from MoS2 to graphene. The nondissipative interlayer charge transfer from MoS2 to graphene is confirmed by density functional calculations. This provides a different platform to further study the photoinduced hot carrier effect in graphene heterostructures for photothermoelectric detectors or hot carrier solar cells.

Investigation of Quantization Effects on RTS Due to Oxide Traps Induced by Channel Hot-Carrier-Stressing in pMOSFETs

Although it is the worst degradation mechanism, the effect of channel hot carrier (CHC) stressing on random telegraph signals (RTS) has not been given enough attention in pMOSFETs. We report on the effect of CHC stressing on different RTS trap parameters namely screened scattering coefficient which controls the amount of charge carrier mobility fluctuations due to remote Coulomb scattering by the trap, RTS fluctuation amplitude, average capture time and capture cross-section. The generation of positive fixed oxide charge with stressing influences the screened Coulomb scattering of the channel carriers and therefore their mobility, in addition to the commonly accepted self-screening of the channel carriers. The two-dimensional mobility fluctuations model is adopted for analyzing the CHC effect on pMOSFETs. The comparison between theoretically and experimentally obtained screened scattering coefficients points toward the impact of the newly generated positive fixed oxide charge due to stressing. The decrease of the screened scattering coefficient results in increased RTS amplitude and decreased contribution of mobility fluctuations to RTS amplitude. Capture time and capture cross-section also change as the capture cross-section pre-factor has been impacted by the reduction of relaxation energy with stressing.

Reversely-Synchronized-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, a reversely synchronized stress (RSS) is proposed to simulate the working condition of switching thin-film transistors (TFTs) in active-matrix displays. The reliability of polycrystalline silicon (poly-Si) TFTs under RSS is characterized and investigated. RSS brings huge device degradation. A dynamic hot carrier (HC) effect, dependent on transition edges of RSS, dominates the degradation. Combined with a transient simulation, the degradation mechanism under RSS in poly-Si TFTs is discussed and developed. To suppress RSS-induced HC degradation, a bridged-grain (BG) structure is employed in the active layer of poly-Si TFTs. Via BG lines’ reducing the lateral electric field in the channel at source/drain sides, the reliability of BG TFTs under RSS is significantly improved.

Photocatalytic production of H2 is a multi-criteria optimization problem: Case study of RuS2/TiO2

Many parameters influence the photocatalytic production of H2. Identifying and quantifying them is necessary for correct comparison of photocatalysts and right understanding of involved mechanism.In this work, we studied the photocatalytic dehydrogenation of isopropanol with titania-supported ruthenium disulfide. We studied the influence of seven parameters on the photocatalytic activity: the temperature, the composition of the reactive mixture, the mass of the photocatalyst, the flux and the energy of the incident photons, the co-catalyst loading and the nature of the support. Their influence was studied, not only on the rate of hydrogen production (or photon yield) but also on the apparent activation energy and on the pre-exponential factor, deduced from an Arrhenius law.The photon yield as a function of the co-catalyst loading show an optimum of activity.A 6.9 % photon yield was obtained at 0.84 wt% and Ephotons=3.65 eV.The rate-determining step for the photocatalytic dehydrogenation of the isopropanol with RuS2/TiO2 is, at optimal conditions, the electron transfer from TiO2 to RuS2. The latter is not favored because of the band diagrams of RuS2 and TiO2. The electron transfer can be optimized working with incident photons having a higher energy, thanks to a hot carrier effect observed in RuS2/TiO2.

Dodecahedral Au/Pt Nanobowls as Robust Plasmonic Electrocatalysts for Methanol Oxidation under Visible-Light Illumination.

Plasmonic nanostructures with large absorption areas under resonant excitation have been utilized extensively in photon-assisted applications. In this work, dodecahedral Au nanobowls were first prepared by an easy and template-free method only through the introduction of H2 PtCl6 and I- during the growth procedure. The Au nanobowls show electron-field enhancement due to the high curvature of the bowl edge, the open region, and dodecahedral morphology. Au/Pt nanobowls, which couple plasmonic Au and catalytic Pt, were then constructed as plasmonic electrocatalysts for methanol oxidation. The mass activity reached 497.6 mA mg-1 under visible-light illumination, which is 1.9 times that measured in the dark. Simultaneously, the electrocatalytic stability is also greatly improved under light excitation. The enhanced properties of the plasmonic Au/Pt electrocatalysts are ascribed to the synergistic effect of the plasmon-enhanced photothermal and hot-carrier effects on the basis of experimental investigations. This work thus offers an effective methodology to construct efficient plasmonic electrocatalysts for fuel cells.

Electrothermal analysis of novel N-P-P FinFET with electrically doped drain: a dual material gate device for reliable nanoscale applications

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.

Editorial Introducing New TDMR Editor Abhisek Dixit

TDMR welcomes Dr. Abhisek Dixit as a new member of the TDMR Editorial Board. Dr. Dixit is an expert on device characterization and modelling of different nanometer technologies, such as bulk Si, PD, and FD-SOI BiCMOS. His experience will be of great help in reviewing and evaluating technical aspects, such as quantum computing hardware, CMOS hot-carrier and radiation effects, pulsed/RF characterization and modelling of advanced FET devices. Dr. Dixit earned his Ph.D. in 2007 from IMEC, Belgium.

Hot carriers perspective on the nature of traps in perovskites

Amongst the many spectacular properties of hybrid lead halide perovskites, their defect tolerance is regarded as the key enabler for a spectrum of high-performance optoelectronic devices that propel perovskites to prominence. However, the plateauing efficiency enhancement of perovskite devices calls into question the extent of this defect tolerance in perovskite systems; an opportunity for perovskite nanocrystals to fill. Through optical spectroscopy and phenomenological modeling based on the Marcus theory of charge transfer, we uncover the detrimental effect of hot carriers trapping in methylammonium lead iodide and bromide nanocrystals. Higher excess energies induce faster carrier trapping rates, ascribed to interactions with shallow traps and ligands, turning these into potent defects. Passivating these traps with the introduction of phosphine oxide ligands can help mitigate hot carrier trapping. Importantly, our findings extend beyond photovoltaics and are relevant for low threshold lasers, light-emitting devices and multi-exciton generation devices.