Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications

Abstract

In this paper, we have investigated the performance of a silicon-based low-doped drain (LDD) SOI-FinFET for the first time and compared it with conventional FinFET for implementation in logic circuits. It is well known that the use of the conventional LDD technology in the triple gate FinFETs reduces the electric field near the drain region and hot carrier effect at the cost of reduced current driving capability as is reported in LDD MOSFETs. We observe a reduction in the peak electric field by 15% near the drain region with a subsequent degradation in the electron velocity, as well. We have presented a semi-analytical approach to model the gate capacitance, drain current, channel potential, and subthreshold slope for the proposed FinFET structure. 3D simulation results for three different channel lengths using the TCAD Sentaurus tool are used to validate the computed results. DC analysis of the LDD-FinFET is performed and results are compared with the conventional FinFET device in terms of threshold voltage, transconductance, and $$I_{\text {ON}}/I_{\text {OFF}}$$ ratio. The capacitance model is used to investigate the subthreshold swing and current driving capability of the proposed device. In addition to this, circuit-level analysis like voltage transfer characteristics and switching characteristic of proposed CMOS inverter using SOI LDD-FinFET is performed. The results presented in this paper can be utilized for the design of low-power digital applications to cater to the requirements of high switching speeds, high gain, and minimum power dissipation.