Drain-induced Barrier Lowering Effect Research Articles

Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions

In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.

Simulation of Novel Nano Low-Dimensional FETs at the Scaling Limit.

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS2 layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS2, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit.

Enhanced performance of normally-OFF GaN HEMTs with stair-shaped p-GaN cap layer

The p-GaN-gated E-mode HEMTs (P-HEMTs) are being extensively studied for emerging power electronics. However, the devices still suffer from performance trade-off among threshold voltage (V TH), output drain current (I DS), and breakdown voltage (V BD). Herein, we propose a P-HEMT with a stair-like p-GaN cap layer to boost their performance. The p-GaN cap layer is composed of four discrete p-GaN staircases with the decreased thickness to the right (Right-Stair P-HEMT) or to the left (Left-Stair P-HEMT). It is found that the RSP-HEMT simultaneously achieves the 1.3 times increased I DS, 160 V enhanced V BD, and improved V TH stability against drain-induced barrier lowering effects, compared with the LSP-HEMT and the conventional BaSeline P-HEMT. These device merits should be attributed to the effective manipulation of the lateral electric field (E F) under all bias conditions by the unique band structures enabled by the RSP configuration. Such E F manipulation strategies offer us helpful guidance and insights to further propel the development of high-performance E-mode P-HEMTs.

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model

Accurate modeling of threshold voltage is necessary in the integrated circuit design of strained silicon devices. Thoroughly researching the factors that affect threshold voltage and establishing a more precise threshold voltage model, can provide essential theoretical support for integrated circuit design. By solving a Poisson equation, in this paper, we demonstrate a comprehensive physical model for the threshold voltage of strained Si NMOSFETs using the gradual channel approximation theory and a quasi-two-dimensional analysis. The model investigates the physical effects such as short-channel, narrow-channel, non-uniform doping, and drain-induced barrier lowering effects on the threshold voltage. After substituting the extracted parameters into the model, a comparison was made with experimental results to validate the accuracy and correctness of the established model. Additionally, variations in the tunneling current of small-sized devices were studied. The two models provide essential references for the analysis and design of strained Si large-scale integrated circuits.

(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs

Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (WFIN) and height (HFIN) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1].Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main concerns when downscaling the MOS transistor [3, 4]. Unlike inversion mode (IM) transistors, the junctionless device is made with a heavily doped silicon layer with the same doping type from source to drain [2, 5]. To lower the series resistance, the source and drain receive an additional doping step to increase their concentration.Although JL transistors are a good alternative for the continuous downscaling of MOS transistors, they still have their basic operation like any other transistor MOSFET. Therefore, it is not completely immune from SCE, such as Drain-Induced Barrier Lowering (DIBL) effect.In this work, a comparison between the DIBL effect in junctionless and inversion-mode nanowire transistors is performed. Experimental results at room and high temperatures are presented for devices with different channel widths.The JL and IM nanowire transistors used in this work were fabricated at CEA-Leti, as described in reference [6]. Devices with 10 parallel channels and channel length (L) of 40 nm and 100 nm were measured, fin width (WFIN) of 12 nm, 17 nm, 22 nm, and 42 nm. Two different values of drain voltage (VD) were applied for all devices, VD1 = 40 mV and VD2 = 800 mV. Finally, the DIBL has been calculated as DIBL=|VT2 – VT1| /(VD2 – VD1). The threshold voltage in both VD has been extracted as described in ref. [7].The analysis for DIBL as a function of fin width is shown in Figure 1(A). For devices with L=100nm, no SCE has been observed and all devices present Subthreshold Slope (SS) close to the theoretical limit. Also, for WFIN up to 22 nm, DIBL is the same both for IM and JL nanowires. When downscaling the length to 40 nm, despite of DIBL increase for all devices, no degradation on SS is seen for JL, whereas IM devices exhibit SS>82mV/dec. Considering reasonable characteristics, i.e., DIBL=100mV/V and S=80 mV/dec [8], except from WFIN=42nm, all JL devices meet these requirements, whereas no IM nanowire with L=40 nm could be used. Even if maximum allowable DIBL were increased to 120mV/V, only the narrowest IM with L=40nm would be acceptable.Aiming to verify the influence of the temperature on the DIBL, Figure 1(B) shows the variation of DIBL in relation to room temperature for IM and JL nanowires with L=100nm and WFIN=12nm, which have similar DIBL at 300K. One can see that DIBL variation with temperature in the IM device is larger than in JL. While the IM transistor presented a DIBL variation of 0.15(mV/V)/K, for the JL one, it is 0.11(mV/V)/K. These results indicate that apart from the good immunity to SCE, JL nanowires are less susceptible to DIBL variation with temperature. Acknowledgements The authors thank financial support from CAPES, CNPq and FAPESP.

Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching.

Negative capacitance field effect transistors made of Hf0.5Zr0.5O2 (HZO) are one of the most promising candidates for low-power-density devices because of the extremely steep subthreshold swing and high open-state currents resulting from the addition of ferroelectric materials in the gate dielectric layer. In this paper, HZO thin films were prepared by magnetron sputtering combined with rapid thermal annealing. Their ferroelectric properties were adjusted by changing the annealing temperature and the thickness of HZO. Two-dimensional MoS2 back-gate negative capacitance field-effect transistors (NCFETs) based on HZO were prepared as well. Different annealing temperatures, thicknesses of HZO thin films, and Al2O3 thicknesses were studied to achieve optimal capacitance matching, aiming to reduce both the subthreshold swing of the transistor and the hysteresis of the NCFET. The NCFET exhibits a minimum subthreshold swing as low as 27.9 mV/decade, negligible hysteresis (∼20 mV), and the ION/IOFF of up to 1.58 × 107. Moreover, a negative drain-induced barrier lowering effect and a negative differential resistance effect have been observed. This steep-slope transistor is compatible with standard CMOS manufacturing processes and attractive for 2D logic and sensor applications as well as future energy-efficient nanoelectronic devices with scaled power supplies.

Study on the effect of 65 nm NMOS transistor using SILVACO TCAD

This work aims to study the effect of the short gate length of 65 nm NMOS transistor using SILVACO TCAD. A 65 nm NMOS was designed and virtually fabricated and characterized using the ATHENA and ATLAS process and device simulators, respectively. A shorter gate length is expected to experience short channel effects (SCE) such as channel length modulation and drain induced barrier lowering (DIBL). The SCE was observed from the comparison of the long gate length (0.3 µm) and short gate length (65 nm) NMOS transistors’ performances. The result observed from the ID-VD graph showed that the 65 nm NMOS experienced the channel length modulation where the drain current, ID did not saturate as VD increased with an increment of 1.45 at VD = 3.3 V. Several improvements were done to overcome the SCE which are retrograde well implantation and Halo implantation. A 5 × 1014 cm−3 Boron of 200 keV implant energy and a 5 × 1013 cm−3 Boron of 100 keV implant energy were implanted for the retrograde well implant which was shown to reduce the channel length modulation effect. In addition, from the ID-VG graph, the drain current for the 65 nm NMOS was not zero when VG = 0 V, which indicated the DIBL effect. The phosphorus of 2 × 1012 cm−3 and 1 × 1013 cm−3 concentration was implanted for the Halo implantation. The results showed that the inclusion of Halo implantation has reduced the DIBL effect as the ID-VG plot showed that ID = 0 when VD = 0 with the threshold voltage, VTH = 1.87 V respectively. This shows that the inclusion of retrograde well implant and Halo implantation reduces the channel length modulation as well as DIBL effect of the short gate length NMOS.

Modeling threshold voltage and drain-induced barrier lowering effect of opposite doping core–shell channel surrounding-gate junctionless MOSFET

For the sake of promoting core–shell channel (CSC) junctionless (JL) MOSFET, this paper models opposite doping core–shell channel (ODCSC) surrounding-gate (SG) JL MOSFET firstly. A model for estimating the threshold voltage and drain-induced barrier lowering (DIBL) effect of ODCSC SG JL NMOSFET by solving Poisson's equation under cylindrical coordinates in different channel regions is presented. The model considers the source/drain extension region beyond the gate edges for different values of the radius of the core channel, the core channel doping, the shell channel doping, gate length, the radius of the total channel, gate and drain biases effectively. The threshold voltage and DIBL are in good agreement with the Sentaurus TCAD simulation results. The results emphasize the function and advantages of the radius of the core channel and core channel doping as additional adjustment parameters to control the threshold voltage and DIBL compared with conventional SG JL NMOSFET. The proposed model of ODCSC SG JL MOSFET will offer a new modeling method of CSC JL devices.

(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.

Combined Influence of Gate Oxide and Back Oxide Materials on Self-Heating and DIBL Effect in 2D MOS2-Based MOSFETs

In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) effect in 2D MoS2-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. The dependence of the DIBL effect and the lattice temperature in the middle of the channel on the gate length is considered for transistors with different gate oxide and back oxide (BOX) materials. The effects of Al2O3 and HfO2 as gate oxide and SiO2 and HfO2 as BOX materials are compared. Transistors, in which the channel is fully and partially (i.e., just below the gate) covered by a gate oxide, are considered. It is shown that the transistors with Al2O3 as gate oxide and SiO2 as BOX materials have higher immunity to DIBL effect and transistors with HfO2 as gate oxide and HfO2 as BOX materials have higher immunity to SHE.

Investigation of Breakdown in Vertical E-Mode Ga2O3 MOSFET with Different Structural Parameters

In order to control drain-induced barrier lowering (DIBL) and thus premature breakdown in enhancement-mode (E-mode) Ga2O3 MOSFETs, the effect of structure and process parameters on the breakdown voltage (VBK) and DIBL is systematically investigated. The results show that the small gate work function, the small oxide dielectric constant, the thick oxide thickness, the excessive doping concentration of the epitaxial layer, and the wide and short channel will lead to a severe DIBL effect, causing the device to breakdown prematurely. On the other hand, the thickness of the drift region has a marginal effect on the DIBL, and after excluding other structural parameters that generate a strong DIBL effect, a reasonable increase in the thickness of the drift region is beneficial to improve the VBK of devices. This study can contribute to the design of Ga2O3 MOSFETs in the application scenario with high VBK reliability requirements.

A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model

Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in power-constrained applications. However, the high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” in memory circuits, the time and storage overhead of conventional simulations based on the Monte Carlo (MC) analysis cannot be tolerated. On the other hand, classic analytical methods predicting failure probabilities from a physical expression become inaccurate in the sub/near-threshold voltage domain due to the hypothetical distribution or the oversimplified drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{ds}$ </tex-math></inline-formula> ) model for nanoscale devices. This work first proposes a simple but efficient empirical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{ds}$ </tex-math></inline-formula> model to describe the drain-induced barrier lowering (DIBL) effect. Based on that, the probability density functions of the interest metrics in SRAM are derived. Two analytical models are then put forward to evaluate SRAM dynamic stabilities, including the access time failure and the write failure. The proposed models can be extended easily to different types of SRAM with different read/write-assist circuits. The models are validated against MC simulations across different operating voltages and temperatures. The average relative errors at 0.5-V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ DD}}$ </tex-math></inline-formula> are only 8.8% for the access-time failure model and 10.4% for the write failure model. The size of the required sample data set is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$43.6\times $ </tex-math></inline-formula> smaller than that of the state-of-the-art method.

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors.

Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (Vbl) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive Vbl countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive Vbl scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.

Analysis of Drain-Induced Barrier Lowering in InGaZnO Thin-Film Transistors

Characterization of short-channel amorphous indium gallium zinc oxide (InGaZnO) (a-IGZO) thin-film transistors (TFTs) has been a crucial issue to realize higher resolution display and heterogeneous integration with complementary metal–oxide–semiconductor (CMOS) technology. In this work, the drain-induced barrier lowering (DIBL) of the a-IGZO TFT was investigated with the variations in oxygen content in the IGZO layer. In order to accurately investigate the effect of the drain voltage on the channel potential, it is necessary to analyze the energy band diagram based on the dopant profile of the channel region. A new method for extracting the channel dopant profile through a simple <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> measurement of the a-TFT sample was proposed. We performed TCAD device simulation based on the extracted density of states and dopant profile of IGZO layer and confirm good agreement with the measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics of a-IGZO TFTs with various oxygen contents. The effective channel length was found to be short with decreasing the oxygen content in the IGZO channel layer. The DIBL effect becomes more severe as the oxygen content decreases. Our methodology, which was successfully verified in this work, can be utilized for the analysis of short-channel effects including DIBL for the scaled a-IGZO TFTs.

A New 4H-SiC Trench MOSFET With Improved Reverse Conduction, Breakdown, and Switching Characteristics

In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N+ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.

A 0.5–1.7 V Efficient and PVT-Invariant Constant Subthreshold gm Reference Circuit in CMOS

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{S}$ </tex-math></inline-formula> , while consuming 1.95 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> .

Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type Dual-bit/cell (NORD) flash cell was studied and fabricated at 55-nm node technology. Both FG- and selected-gate (SG-) length, for the first time, were scaled down to sub-80 nm and sub-60 nm in NORD flash, respectively. In this paper, performance of aggressively scaled cells were demonstrated by measurements. Firstly, the cell’s characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor had been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pocket implants for the half-isolated FG-channel. Thirdly, reading biases were also studied to expand the window of read currents. A novel cell structure was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area. Finally, the reliability characteristics were also presented.