Drain-induced Barrier Lowering Effect Research Articles

The threshold-voltage model of MOSFET devices with localized interface charge

A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases.

Subthreshold current model with modified threshold voltage for submicrometre scale GaAs MESFETs

A new analytical two-dimensional model is developed that accurately predicts channel potential variation with external voltages and along the length of the channel in the subthreshold regime, including drain-induced barrier lowering (DIBL) effects in GaAs MESFETs. Threshold voltage is modified to account for short channel effects. The parameters important for the modelling of subthreshold drain current are calculated and this provides the basis for a subthreshold current model. Moreover, the developed analytical models are compared with those of Adams and numerical analysis and good agreement is obtained.

Punchthrough currents in sub-micron short channel MOS transistors

The punchthrough current in sub-micron MOS transistors is essentially initiated at the surface near the edge of source junction. A surface diffusion current ( I sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending ( Δφ so). The DIBL effect increases with decreasing channel length. In addition, the extracted Δφ so from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long sub-micron devices (≈0.62 μm) to the strong-inversion mode for deep sub-micron devices (≈0.12 μm). For intermediate sub-micron devices (≈0.37 μm), I sdif eventually converts to the bulk space-charge-limited current ( I scl) as the connected source/drain depletion region expands with increasing drain bias. For long sub-micron devices only I sdif dominates, while for deep sub-micron devices it converts rapidly to I scl in the bulk depletion regions over the drain bias range investigated.

A 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFETs

A two-zone Green's function solution method is proposed to analytically model the potential distribution in the silicon film of fully depleted SOI MESFETs, in which the exact solution of 2-D Poisson's equation is obtained by using the appropriate boundary conditions. From the derived analytic 2-D potential distribution, the bottom potential in the active silicon film is used to analyze the drain-induced barrier lowering effect and the threshold voltage is defined in terms of minimum channel potential barrier. The results of the developed analytic threshold-voltage model are compared with those of 2-D numerical simulation, and good agreements are obtained for the gate length down to 0.1 /spl mu/m with wide ranges of structure parameters and bias conditions.

Temperature dependence of drain-induced barrierlowering in deep submicrometre MOSFETs

A new method for extracting the drain-induced barrier lowering (DIBL) parameter in an MOS transistor is proposed. This method is used to study the influence of temperature on the DIBL effect. It is found that the DIBL parameter is almost independent of temperature between 50 and 300K. This method makes it also possible to recalculate the intrinsic output characteristics that the device would have in the absence of DIBL, and, in turn, to evaluate the intrinsic device saturation parameters.

Physical phenomena and limitations in submicrometer MOSFETs

In the drive towards greater integration as occasioned by VLSI, MOS device dimensions and technology are scaled down appropriately into the submicron range. This paper analyses the physical and technological limitations for MOS VLSI arising from down-scaling. Specifically, drain-induced barrier lowering, velocity saturation and subthreshold temperature sensitivity effects are examined quantitatively. The results suggest that there may well be a minimum useful size beyond which scaling may not yield strong improvements of device performance.

A New Recessed Channel Metal-Oxide-Semiconductor Field-Effect Transistor with Selectively Halo-Doped Channel and Deep Graded Source/Drain

To improve the performance and reliability of deep submicron metal-oxide-semiconductor (MOS) devices, we propose a gate-recessed metal-oxide-semiconductor field-effect transistor (GR-MOSFET) which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counter-doping. The GR-MOS structure eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot carrier effect which are most important in deep submicron device design. It also reduces the V T lowering effect and lateral electric field at the drain. The fabricated 0.25 µm GR-MOSFET with a 10 nm gate oxide has exhibited 15% higher transconductance, more than 20% increased saturation current at V D=V G=3 V, 1 V higher BV DSS and 6 times less substrate current compared with a LDD-MOSFET of same device dimension.

A new 0.25- mu m recessed-channel MOSFET with selectively halo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V/sub T/ lowering effect and the lateral electric field at the drain. A 0.25- mu m GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V/sub D/=V/sub G/=3.3 V, 1 V higher BV/sub DSS/, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions. >

Short-channel effects and drain-induced barrier lowering in nanometer-scale GaAs MESFET's

Short-channel effects in GaAs MESFETs are investigated. MESFETs were fabricated with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers. The MESFETs were characterized by DC transconductance, output conductance, and subthreshold measurements. This work focuses on overcoming the short-channel effect of large output conductance by the inclusion of an AlGaAs buffer layer, and identifying the benefit the AlGaAs buffer affords for reducing subthreshold current, including the effect of drain-induced barrier lowering. The design yielded 300-nm gate-length MESFETs with excellent suppression of the major short-channel effects. >

An ultra-shallow buried-channel PMOST using boron penetration

A novel process using controlled boron penetration to form an ultrashallow buried-layer for a sub-half-micrometer channel-length n/sup +/ polysilicon-gate PMOS device is presented. Experimental results coupled with two-dimensional process and device simulation are used to examine the impact of the buried-channel design on the drain-induced barrier lowering effects. Using a sacrificial 125-AA gate oxide and a BF/sub 2/-implanted polysilicon layer, the boron penetration profile is formed prior to the actual gate oxidation. This process is suitable for sub-half-micrometer channel-length n/sup +/ poly-gated CMOS technologies which require gate oxide thicknesses of less than 100 AA. >

A theoretical model for the current-voltage characteristics of a floating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell. >

A new 2-D analytic threshold-voltage model for fully depleted short-channel SOI MOSFET's

The exact solution of the 2-D Poisson equation for fully depleted SOI MOSFETs is derived by using a three-zone Green's function solution technique. Based on the derived 2-D potential distribution, the front and back surface potential distributions in the Si film are analytically obtained and their accuracies are verified by 2-D numerical analysis. The calculated minimum surface potential and its location are used to analyze the drain-induced barrier-lowering effect and further to develop an analytic threshold-voltage model. Comparisons between the developed analytic threshold-voltage model and the 2-D numerical analysis are made. It is shown that excellent agreements are obtained for wide ranges of device structure parameters and applied biases. >

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 mu m is improved for the range of L 1.2 mu m, but is worse for L between 0.6 and 1.2 mu m. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V/sub TH/ as required for room-temperature operation are briefly discussed. >

Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, an empirical model for describing this substrate bias characteristic of the DIBL effect is developed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analytical study of punchthrough in buried channel P-MOSFETs

The punchthrough phenomenon in buried-channel (BC) P-MOSFETs (p-metal oxide-semiconductor field effect transistors) depletion-mode devices is investigated analytically using the voltage-doping transformation (VDT) technique. The resulting punchthrough current model shows a high degree of accuracy over a wide range of biases and channel lengths while still retaining the simplicity required for CAD (computer-aided-design) models. The mean error over about 300 experimental current-voltage points is as small as 3%. The mechanism of punchthrough in a BC-P-MOSFET is shown to be due to the DIBL (drain-induced barrier lowering) effect, which is further shown to be considerably enhanced by two effects. These effects, a surface inversion layer screening (SILS) and a drain-induced channel enlargement (DICE), are deduced and investigated analytically. The methods leading to a suppression of these effects are shown. Owing to its accuracy and generality, the present punchthrough analysis is expected to find applications in design and process optimization as well as in the simulation of advanced BC-P-MOSFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new approach to analytically solving the two-dimensional Poisson's equation and its application in short-channel MOSFET modeling

An analytical solution for the potential distribution of the two-dimensional Poisson's equation with the Dirichlet boundary conditions has been obtained for the MOSFET device by using Green's function method and a new transformation technique, in which the effects of source and drain junction curvature and depth are properly considered. Based on the calculated potential distribution, the subthreshold current considering the drain-induced barrier lowering effects has been computed by a simple current equation that considers only the diffusion component with an effective length determined by the potential distribution at the SiO 2 -Si interface. From the calculated subthreshold current, the threshold voltage of the MOSFET's is determined. It has been verified that the dependences of the calculated threshold voltage and subthreshold current on device channel length, drain, and substrate biases are in good agreement with those computed by whole two-dimensional numerical analysis and experimental data.

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions. The validity of these published expressions has not been verified so far for small-geometry devices of different parameters. Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature. In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current. Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values. Hence we determined a set of new geometry parameters η and B/A for the DIBL threshold relationship that can be used with the analytical model. Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required. Also, our results should be useful for calibrating existing analytical MOSFET models. In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices.

Influence of drain-induced barrier lowering on the dynamic conductance of short-channel MOSFETs

An analysis of the influence of drain-induced barrier lowering (DIBL) on the dynamic conductance of short-channel MOSFETs is presented. A new method of determination of surface state density Nss from the normalised dynamic conductance characteristics is proposed. The method is extended to the case of very short-channel devices to account for DIBL effects.

Transistor scaling with constant subthreshold leakage

A model for scaling transistors with constant subthreshold leakage is presented. In contrast with other scaling theories, the scaling formulation presented does not necessarily lead to transistors with long channel characteristics. Instead, the transistor is scaled only to enhance circuit performance while meeting circuit specifications-in this case, subthreshold leakage current. The model is critically dependent upon the drain induced barrier lowering effect which has been evaluated as a function of channel length, gate thickness, and channel doping. The effect is found to vary as L^{-m} where m = 1.2-1.4 .