Abstract
A novel process using controlled boron penetration to form an ultrashallow buried-layer for a sub-half-micrometer channel-length n/sup +/ polysilicon-gate PMOS device is presented. Experimental results coupled with two-dimensional process and device simulation are used to examine the impact of the buried-channel design on the drain-induced barrier lowering effects. Using a sacrificial 125-AA gate oxide and a BF/sub 2/-implanted polysilicon layer, the boron penetration profile is formed prior to the actual gate oxidation. This process is suitable for sub-half-micrometer channel-length n/sup +/ poly-gated CMOS technologies which require gate oxide thicknesses of less than 100 AA. >
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