Drain-induced Barrier Lowering Effect Research Articles

Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Performance Evaluation of Silicon Nanowire Gate-All-Around Field-Effect Transistors and Their Dependence of Channel Length and Diameter

The performance of a semiconducting Silicon Nanowire (SiNW) Gate-All-Around (GAA) transistors as basic logic gates are assessed and tabulated for certain metric, against those of metal-oxide-semiconductor fieldeffect transistors (MOSFETs). Both SiNW and nano-MOSFET models agree considerably well with the trends available in experimental data. The simulation results show that silicon nanowire can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of SiNWFET and MOSEFET, namely propagation delay, energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. In addition, the influence of nanowire channel length and diameter over drain-induced barrier lowering (DIBL) and substhreshold swing (SS) in SiNWFET are also explored and compared with other experimental data. It has been shown that the SiNWFET model has a lower power-delay product (PDP) and energy-delay product (EDP) than of the 32 nm MOSFET Predictive Technology Model (PTM) in the circuit simulations. Shorter length and smaller diameter nanowire are desired to suppress short channel effects. Ultimately, SiNWFET have superior performance compared to nano-MOSFET due to the nearly ideal carrier transport in quasi-one dimensional structure.

Analytic compact model of ballistic and quasi-ballistic transport for cylindrical gate-all-around MOSFET including drain-induced barrier lowering effect

We propose an analytic compact model of drain current in the ballistic and quasi-ballistic modes for cylindrical gate-all-around MOSFETs incorporating drain-induced barrier lowering (DIBL) effect. The model is based on our previous work addressing an analytic compact model for all operation regions, where electrostatic potential profile along the channel has not been taken into account. In this paper, we introduce variation of electrostatic potential along the channel to model the DIBL effect in the subthreshold region. The resulting analytic compact model is tested against TCAD simulation, and good accuracy is demonstrated.

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device Vth is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.

Effect of drain-induced barrier lowering on performance of ultralow-supply-voltage CMOS circuits operating in subthreshold region

The effects of drain-induced barrier lowering (DIBL) on the performance characteristics of devices and circuits operating in the subthreshold region are evaluated by measurement and simulation. It is found that the measured drain current markedly decreases in the presence of a large DIBL at supply voltage (Vdd) in the subthreshold region such as 0.3 V. In addition, the simulated propagation delay of ring oscillators is more degraded in the subthreshold region as DIBL increases even though the on-current (Ion) is the same in all the devices, and the calculated energy consumption increases with DIBL in the subthreshold region. It is concluded that DIBL should be suppressed in the design of subthreshold CMOS circuits.

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast ID-VG and modulated peak/base pulse time ID-VD measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

A 700 V narrow channel nJFET with low pinch-off voltage and suppressed drain-induced barrier lowering effect

This paper proposes a 700V narrow channel region triple-RESURF (reduced surface field) n-type junction field-effect transistor (NCT-nJFET). Compared to traditional structures, low pinch-off voltage (VP) with unobvious drain-induced barrier lowering (DIBL) effect and large saturated current (IDsat) are achieved. This is because p-type buried layer (Pbury) and PWELL are introduced to shape narrow n-type channel in JFET channel region. DIBL sensitivity (SDIBL) is firstly introduced in this paper to analyze the DIBL effect of high-voltage long-channel JFET. Ultra-high breakdown voltage is obtained by triple RESURF technology. Experimental results show that proposed NCT-nJFET achieves 24-V VP, 3.5% SDIBL, 2.3-mA IDsat, 800-V OFF-state breakdown voltage (OFF-BV) and 650-V ON-state breakdown voltage when VGS equals 0V (ON-BV).

Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.

Simulation of electrical characteristics and structural optimization for small-scaled dual-gate GeOI MOSFET with high-k gate dielectric

The influences of the main structure and physical parameters of the dual-gate GeOI MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium (Ge) channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect (SCE) and drain-induced barrier lowering (DIBL) effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10–18 nm and (5–9) × 1017 cm−3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8–1 nm and 15–30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved: on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1 μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV.

Anomalous drain‐induced barrier lowering effect of thin‐film transistors due to capacitive coupling voltage of light‐shield metal

The anomalous drain-induced barrier lowering (DIBL) effect of long-channel thin-film transistors (TFTs) with a light shield (LS) is investigated by two-dimensional (2D) device simulation. In long-channel TFTs with a LS, which is long enough to neglect the DIBL effect and the floating body effect, a decrease of threshold voltage (V th) was observed at high drain voltages. The V th lowering is due to the large potential of the LS induced by the high drain voltage, which lowers the height of the source potential barrier. It is found that the LS-induced DIBL effect can be larger as the length of the LS increases or the thickness of the buried oxide decreases.

Total-Ionizing-Dose Induced Coupling Effect in the 130-nm PDSOI I/O nMOSFETs

The tolerance of partially depleted (PD) silicon-on-insulator nMOSFETs to total-ionizing-dose-induced trapped charge in the buried oxide is investigated. The radiation-induced coupling effect due to the metamorphosis of PD device into a fully depleted one is observed. The coupling effect is responsible for the negative threshold voltage shift, enhanced drain-induced barrier lowering effect, subthreshold slope increase, and transconductance variation in the front channel device. The back channel implantation is introduced as an effective way to suppress the radiation-induced coupling effect.

New analytical models of subthreshold surface potential and subthreshold current of fully depleted short-channel silicon-on-insulator MOSFETs with halo or pocket implantation

New analytical models of the subthreshold surface potential, threshold voltage and subthreshold current of fully depleted (FD) silicon on insulator MOSFETs with halo or pocket implants are presented. The subthreshold surface potential model is based on the solutions of the quasi-two-dimensional (2D) Poisson’s equation, which rigorously satisfy the boundary conditions of the continuity of the potential and electric field in the lateral direction along the channel surface of halo MOS transistors. Closed-form model equations without any fitting empirical formula correctly and efficiently generate the surface potential distribution between the source and drain regions. The drain-induced barrier lowering effect of deep-submicrometer halo MOSFETs is also addressed in the present models. On the basis of the subthreshold surface potential, analytical models of the threshold voltage and subthreshold current are also developed for deep-submicrometer halo MOSFETs. The subthreshold current model is derived using the conventional drift-diffusion current theory considering the nonuniform doping profiles of a silicon film of fully-depleted silicon-on-insulator (SOI) MOS devices with halo implants. The results obtained using the model have been compared with those obtained using the device simulation software Medici to show the validity of the proposed model, and good agreement is achieved between the two. The use of the presented models can be treated as an alternative to 2D numerical analysis and used for the design of deep-submicrometer FD SOI MOSFETs with halo or pocket implants.

The impact of quantum confinement on the electrical characteristics of ultrathin-channel GeOI MOSFETs

The impact of quantum confinement on the electrical characteristics of ultrathin-channel GeOI n-MOSFETs is investigated on the basis of the density-gradient model in TCAD software. The effects of the channel thickness (Tch) and back-gate bias (Vbg) on the electrical characteristics of GeOI MOSFETs are examined, and the simulated results are compared with those using the conventional semi-classical model. It is shown that when Tch > 8 nm, the electron conduction path of the GeOI MOSFET is closer to the front-gate interface under the QC model than under the CL model, and vice versa when Tch < 8 nm. Thus the electrically controlled ability of the front gate of the devices is influenced by the quantum effect. In addition, the quantum-mechanical mechanism will enhance the drain-induced barrier lowering effect, increase the threshold voltage and decrease the on-state current; for a short channel length (≤ 30 nm), when Tch > 8 nm (or < 8 nm), the quantum-mechanical mechanism mainly impacts the subthreshold slope (or the threshold voltage). Due to the quantum-size effect, the off-state current can be suppressed as the channel thickness decreases.

Investigation of channel width-dependent threshold voltage variation in a-InGaZnO thin-film transistors

This Letter investigates abnormal channel width-dependent threshold voltage variation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Unlike drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, the wider the channel, the larger the threshold voltage observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider channel devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast IV measurement is utilized to demonstrate the self-heating induced anomalous channel width-dependent threshold voltage variation.

A Unified Drain–Current Model of Silicon Nanowire Field-Effect Transistor (SiNWFET) for Performance Metric Evaluation

The critical dimensions of silicon-based devices have reached below 100 nm length scale. In order to overcome short channel effects due to downscaling, research and development of new structures and materials is crucial. With improved gate control, silicon nanowire (SiNW) is a promising candidate in scaled-down field-effect transistors (FETs) that can replace the conventional silicon complementary metal-oxide semiconductor (CMOS) bulk-devices. A unified drain current (I-V) model of SiNW incorporating velocity saturation effects is presented as an alternative approach in controlling the ultimate drift saturation and charge carrier mobility. Our results reveal that SiNWFET can significantly reduce drain-induced barrier lowering (DIBL) effect and subthreshold swing (SS) as well as provide a high on-off current ratio (I-on/I-off). The enhancement can be achieved by reducing the oxide thickness (T-OX) and increasing the diameter (T-si)channel length (L) and doping concentration (N-d). The investigation provides significant insight into the device performance of SiNWFET in electronic applications.

Two-dimensional analytical models for the symmetrical triple-material double-gate strained Si MOSFETs

A novel double-gate strained Si metal-oxide-semiconductor field-effect transistor (MOSFET), in which the top and bottom gates consist of three laterally contacting materials with different work functions, is proposed in this paper. The two-dimensional (2D) analytical models for the surface potential, surface electric field and threshold voltage are presented. The effects of Ge fraction on surface potential, surface electric field and threshold voltage are investigated. The effects of the triple-material length ratio on threshold voltage and drain induced barrier lowering are discussed. The characteristics of the device are studied by comparing with those of the single-material double-gate MOSFETs. The results show that the structure can increase the carrier transport speed and suppress the drain induced barrier lowering effect. The three-material gate length ratio is optimized to minimize short-channel effect and drain induced barrier lowering effect.

A Novel Quasi-3-D Threshold Voltage Model for Fully Depleted Quadruple-Gate (FDQG) MOSFETs: With Equivalent Number of Gates (ENG) Included

Instead of solving the three-dimensional (3-D) Poisson's equation, we present a novel quasi-3-D threshold voltage model for fully depleted quadruple-gate (QG) MOSFETs based on the minimum central potential derived from the quasi-3-D scaling equation. Accounting for short-channel effects (SCEs) on the device, the natural length of the QG FET in the scaling equation is obtained from the equivalent number of gate equation of 1/ λQG2 = 1/ λDG12+1/ λDG22, where the QG device working in x-y-z space with natural length of λQG can be broken into two equivalent double-gate (DG) FETs with natural lengths of λDG1 and λDG2 working in y-z and x-z planes, respectively. Numerical simulation data for threshold voltage roll-off and drain-induced barrier lowering effects (DIBL) were compared to the model to validate the formula. Among QG FETs with the same perimeters, one with a square cross section will show the worst immunity to SCEs due to the largest natural length. With the criterion of DIBL≤50 mV, an improvement of up to 30% is illustrated in the minimum channel length for the QG MOSFET in comparison to the DG MOSFET.

Enhanced Radiation Sensitivity in Short-Channel Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors

The total ionizing dose effects of partially depleted silicon-on-insulator (SOI) transistors in a 0.13 μm technology are studied by 60Co γ-ray irradiation. Radiation enhanced drain-induced barrier lowering (DIBL) under different bias conditions is related to the parasitic bipolar in the SOI transistor and oxide trapped charge in the buried oxide, and it is experimentally observed for short channel transistors. The enhanced DIBL effect manifests as the DIBL parameter increases with total dose. Body doping concentration is a key factor affecting the total ionizing dose effect of the transistor. The low body doping transistor exhibits not only significant front gate threshold voltage shift as a result of the coupling effect, but also great off-state leakage at high drain voltage due to the enhanced DIBL effect.

Poly-silicon thin-film transistors without active layer pattern for high current performance with large operational range

We report the effect of thin-film transistors (TFTs) without an active pattern (TFTs w/o an active pattern) on the improvement of the drain current and on the reduction of the drain-induced barrier lowering (DIBL) effect. The electrical characteristics of TFTs w/o an active pattern are immensely different from those of normal TFTs because they are composed of a channel area with wholly preserved excimer laser annealing processed poly-silicon (poly-Si) and a specially designed gate electrode. An un-etched poly-Si layer can be utilized as a channel region by designing the gate metal. The extended electric field following the shape of the gate electrode increases the drain current by six to seven times compared to that of normal TFTs. Furthermore, the extended channel area can reduce the DIBL effect considerably. Since the un-etched poly-Si layer has no sharp slope angles or tips on the edge of the precursor, TFTs w/o an active pattern are highly resistant to breakdowns of the gate insulator. Finally, the reducing photo-lithography process on the precursor layers of TFTs effectively simplifies back-plane fabrication.

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (IOFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (ION/IOFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.