Abstract
In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (IOFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (ION/IOFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.
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