Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Avi Karsenty,Avraham Chelly

doi:10.1155/2015/609828

Abstract

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Highlights

The Drain-Induced Barrier Lowering (DIBL) effect is a well-known phenomenon, which was reported in different types of nanoscale devices, such as in classical short-channel MOSFET devices [1] and recently in long-channel Carbon Nano Tubes (CNT) devices [2].The DIBL effect was mainly reported in short channel structures
We report the evidence of an anomalous DIBL effect in nanoscale n-type Fully Depleted- (FD-)SOI MOSFET with a Gate-Recessed Channel (GRC) thickness of 2.2 nm and a long channel W/L ratio of 80/3 [μm]
The transfer (IDS-VGS) characteristics of the n-type Fully-Depleted Silicon-OnInsulator (FD-SOI) MOSFET were measured at room temperature (300 K) and shown in Figure 2 in a semilog scale for several VDS voltages (1, 2, 3, and 4 V)

Summary

Introduction

The Drain-Induced Barrier Lowering (DIBL) effect is a well-known phenomenon, which was reported in different types of nanoscale devices, such as in classical short-channel MOSFET devices [1] and recently in long-channel Carbon Nano Tubes (CNT) devices [2]. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (VT) a function of the length of the channel. The gate voltage required to form the channel is lowered, and VT decreases with an increase in VDS This effect is called Drain-Induced Barrier Lowering. We report the evidence of an anomalous DIBL effect in nanoscale n-type FD-SOI MOSFET with a Gate-Recessed Channel (GRC) thickness of 2.2 nm and a long channel W/L ratio of 80/3 [μm].

Experimental Results and Analysis

Interpretation

Conclusion