Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

Abstract

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, an empirical model for describing this substrate bias characteristic of the DIBL effect is developed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>