Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 K

Abstract

Experimental results on the substrate biasing characteristics of drain-induced barrier lowering (DIBL) in short channel PMOS devices with boron ion channel doping at 77 K are presented in detail. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and thereafter began decreasing. The new version of the two-dimensional device simulation program, MINIMOS 4.0, suitable for MOS simulation at cryogenic temperatures, was used to investigate this unique feature, which could be explained as the transition of surface DIBL to subsurface DIBL and the onset of punch-through. A new empirical model for describing the substrate characteristics of DIBL was developed: R = δV TH(DIBL)/ δV DS = αL − β , α = α o + α 1 V BS, β = β O + β 1 V BS. It is used for quantitative comparisons between 300 and 77 K based on the test PMOS device measurements. The extracted values of α O and α 1 (representing δV DIBL at V BS = OV and the slope of R versus V BS for the L = 1 μm device) were decreased by 27.5% and increased by 42%, respectively, from 300 to 77 K. The corresponding values of β 0 and β 1 (representing the curvature of δV DIBL versus L at V BS = OV and the slope of this curvature versus V BS) were decreased by 9 and 4%, respectively, for the same temperature reduction. These results clearly show the improvement of DIBL at 77 K, especially for smaller V BS, and could be explained physically by the decrease of the source (drain)-to-channel depletion width and partial carrier freeze-out effect in the substrate. Further simulations were carried out by MINIMOS 4.0 with the emphasis on the boron ion channel doping profile. By changing the channel implantation dose from 4.3 × 10 11 to 8.7 × 10 11 cm −2 and energy from 25 to 35 keV, the extracted parameters of α and β were found to be very sensitive to both implantation dose and energy.