The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K

Abstract

This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: (R) = δV TH (DIBL) δV DS = αL −β , α = α 0 + α 1 V BS, β = β 0 + β 1 V BS has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters α and β were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.