Study on the effect of 65 nm NMOS transistor using SILVACO TCAD

Abstract

This work aims to study the effect of the short gate length of 65 nm NMOS transistor using SILVACO TCAD. A 65 nm NMOS was designed and virtually fabricated and characterized using the ATHENA and ATLAS process and device simulators, respectively. A shorter gate length is expected to experience short channel effects (SCE) such as channel length modulation and drain induced barrier lowering (DIBL). The SCE was observed from the comparison of the long gate length (0.3 µm) and short gate length (65 nm) NMOS transistors’ performances. The result observed from the ID-VD graph showed that the 65 nm NMOS experienced the channel length modulation where the drain current, ID did not saturate as VD increased with an increment of 1.45 at VD = 3.3 V. Several improvements were done to overcome the SCE which are retrograde well implantation and Halo implantation. A 5 × 1014 cm−3 Boron of 200 keV implant energy and a 5 × 1013 cm−3 Boron of 100 keV implant energy were implanted for the retrograde well implant which was shown to reduce the channel length modulation effect. In addition, from the ID-VG graph, the drain current for the 65 nm NMOS was not zero when VG = 0 V, which indicated the DIBL effect. The phosphorus of 2 × 1012 cm−3 and 1 × 1013 cm−3 concentration was implanted for the Halo implantation. The results showed that the inclusion of Halo implantation has reduced the DIBL effect as the ID-VG plot showed that ID = 0 when VD = 0 with the threshold voltage, VTH = 1.87 V respectively. This shows that the inclusion of retrograde well implant and Halo implantation reduces the channel length modulation as well as DIBL effect of the short gate length NMOS.