Double Gate Tunnel Field Effect Research Articles

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (I ON), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional I ON, I ON/I OFF ratio, and minimal sub-threshold swing (S) of ∼3.04 × 10−4 A μm−1, ∼1.2 × 1010, and ∼3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ∼0.75 mS/μm, ∼0.97 THz, and ∼102 GHz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ∼1.7 × 10−15 A μm−1 to 2.4 × 10−10 A μm−1 with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

This research paper investigates the application of a Double Gate (DG) Tunnel Field-Effect Transistor (DG-TFET) for the detection of cell lines derived from breast cancer tissue, namely Hs578T, MDA-MB-231, MCF-7, and T47D. The device incorporates two nanocavities positioned beneath the two gate electrodes, significantly enhancing detection capabilities. The study emphasizes the differentiation between healthy non-tumorigenic cells (MCF-10A) and breast cancer-derived cell lines by incorporating gate engineering into the TFET. Furthermore, the research explores the impact of changes in dielectric values specific to different breast malignant cell types on the biosensor's detection capabilities. Additionally, the investigation delves into the influence of variations in device geometry, including cavity dimensions and dielectric layer thickness, on critical parameters such as drain current sensitivity, transconductance sensitivity, and ION/IOFF sensitivity. Sensitivity analysis concerns drive current, ION/IOFF ratio, threshold voltage (Vth), and transconductance. The structural design of the device is tailored to facilitate array-based diagnosis and screening of cell lines derived from breast cancer tissue. This design offers several advantages, including a simplified transduction process, compatibility with CMOS processes, cost-effectiveness, reproducibility, and adjustable electrical responses. The researchers employed ATLAS, a two-dimensional (2D) device simulator from Silvaco, to model and define the device structure. The numerical simulations validate the device's performance, demonstrating favorable ON-OFF transition profiles.

A Mg2Si/Si heterojunction based dielectric modulated dopingless TFET biosensor for label free detection

In this work, we contrasted the potential of Mg2Si/Si heterojunction-based dopingless (DL) double gate tunnel field effect transistor (DGTFET) with conventional (C)-DL-DGTFET. The simulation results exhibit excellent capabilities of Mg2Si source DL-DGTFET in terms of electrical properties, that are ION, ION/IOFF, electron tunnelling rate, Vth and SS in comparison to C-DL-TFET. A remarkable improvement of 77.5 % and 81.3 % is observed while computing Vth and SS, in the case of Mg2Si source DL-DGTFET. For that reason, to avail most advantage of Mg2Si/Si heterojunction, the proposed device with similar specifications and dimensions is critically analysed for biosensing applications. Dual cavities (20 nm x 5 nm) are carved underneath gate electrodes near source channel junction to grab the biomolecules. The proposed biosensor (Mg2Si source DL-DGTFET) exhibits significant sensitivity results for both charged (deoxyribonucleic acid (DNA)) and uncharged (neutral) biomolecules. Also, we have reported an impact on biosensor sensitivity with variation in the height of nanocavity (tbio). The effect of steric hindrance on sensitivity is analysed by considering four step profiles - increasing, decreasing, convex and concave. The result reveals the competency of Mg2Si/Si heterojunction DL-DGTFET in terms of overall device sensitivity.

Analytical modelling and reliability analysis of charge plasma-assisted Mg2Si/Si heterojunction doping less DGTFET for low-power switching applications

Fabrication of tunnel field effect transistor (TFET) confronts various challenges, one of which is random dopant fluctuation (RDF), which diminishes the benefits associated with low subthreshold swing (SS) and high ION/IOFF ratio. By conducting physics-based 2D analytical modelling, this paper proposes a magnesium silicide/silicon (Mg2Si/Si) heterojunction-based doping less double gate tunnel field effect transistor (HB-DL-DGTFET). This work utilizes the concept of charge plasma to tackle the issues of RDF. The analytical analysis in this study is based upon the determination of the center-channel potential by solving 2D Poisson’s equation, considering appropriate boundary conditions. Here, surface potential, electric field, energy bands, drain current and threshold voltage are extracted mathematically. In addition to the aforementioned parameters, several other analog performance parameters like transconductance, drain conductance, device efficiency, intrinsic gain, output resistance and channel resistance have also been studied in this context. The analytical findings have been duly validated using the ATLAS TCAD device simulator. Furthermore, this work focuses on exploring proposed device reliability through an investigation of, the influence of interface trap charges (ITC), present at the Si/SiO2 interface. The study analyses ITC's impact on analog performance and the obtained results are compared with that of conventional doping less DGTFET (C-DL-DGTFET). The simulation results reveal that HB-DL-DGTFET exhibits greater immunity against ITC. Thus, validating the potential of HB-DL-DGTFET as a superior candidate for low-power switching applications.

Ge‐ and Ge1−zSnz‐Based Gate‐Underlap Dual Material Double Gate Tunnel Field Effect Transistor: Modeling, Optimization, and its Application to Biosensors

Herein, an n‐channel dual material double gate tunnel field effect transistor (DMDG‐TFET) with a gate–drain underlap using Ge and Ge1−zSnz is proposed. An analytical model has been developed to optimize the length of the underlap region for Ge and Ge–Sn alloy as the channel material. The ambipolarity shown by TFET has been utilized to perform a label‐free biosensing in response to the change of permittivity of the biomaterials used in the gate–drain underlap region. The use of Ge–Sn alloy as a channel material results in a lower ambipolar current but higher sensitivity to the presence of biomolecules. DMDG with workfunction (4 and 4.4 eV) is used to optimize the device performance. The analytical results have been validated by the results obtained using commercial software (Silvaco TCAD). A high sensitivity of the biosensor device is obtained by utilizing the tunnel FET ambipolar current with optimized gate underlap of LUD = 55 nm (for Ge) and LUD = 38 nm (for Ge–Sn alloy).

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

Performance Analysis of Reverse T-Shaped Tunnel Field Effect Transistor (RT-DG-TFET) Based Lable–Free Dielectric Modulation Detection of SARS-CoV-2 Virus

In this paper the performance of Reverse T-Shaped Double gate Tunnel field effect transistor is investigated (RT-DG-TFET)with respect to different bio molecules for application as biosensor. The proposed device is built in order to overcome the limitations of short channel effects (SCEs) in MOSFET devices. The recent outbreak due to Corona virus demanded the requirement of a lable free, highly sensitive, quick and meticulous biosensor for the detection of SARS-CoV-2 virus. This device study records the lable free electrical detection of SARS-CoV-2 virus using RT-DG-TFET that detects the virus because of the electrical properties (dielectric constant) of different bio molecules like protein, biotin, air, strepta, APTES, DNA etc. These are studied by using different dielectric modulation techniques in biosensor application. The etched nano-cavity implanted under the gate electrode first immobilizes the SARS-CoV-2 virus, which is subsequently used to identify it. The sensitivity and different analog/RF parameters are also investigated for different bio molecules. All these simulations are investigated in TCAD Sentaurus simulator.

Source material valuation of charge plasma based DG-TFET for RFIC applications

This paper seeks to present a comprehensive analysis to check the viability of four different source materials in a charge plasma-based double gate tunnel field effect transistor (CP-DGTFET) as RF/microwave systems components. This work aims to provide a comparative study of the electrical and analog parameters of three devices (labeled as D-II, D-III, D-IV) with Si0.5Ge0.5, Ge, Mg2Si as the source material with a conventional Si source homojunction CP-DGTFET (referred as D-I). In addition, linearity and distortion are investigated. The selection of the source material illustrates the effect on the band structure at heterojunctions, as a combined effect of low bandgap and electron affinities of the material used. Results obtained through numerical simulations show that the device D-IV with Mg2Si source shows excellent performance parameters with maximum I ON (4.6 × 10−3 A µm−1) and minimum V th (0.26 V). Also, the switching ratio (1013) and SS (10.89 mV/decade) offered by D-IV is the best among all four devices investigated. Various linearity FOM’s viz. transconductance and its higher order derivatives (g m , g m2 , g m3), higher order voltage intercept points (V IP2 , V IP3), third-order intercept input power, third-order intermodulation distortion, 1 dB compression point, 2nd and 3rd order harmonic distortion, and total harmonic distortions (THD) have also been examined. All of this research was carried out using the Atlas Silvaco simulation tool. This study reveals that the Mg2Si source CP-DGTFET is best suited for high-frequency, low-power and high linearity applications in modern communication systems.

Design and Implementation of Negative Capacitance Based Electrostatic Doped Double Gate Tunnel Field Effect Transistor

Design and Implementation of Negative Capacitance Based Electrostatic Doped Double Gate Tunnel Field Effect Transistor

Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).

Analytical modeling of subband quantization and quantum transport in very Low-dimensional dual metal double gate TFET

We present a novel and comprehensive quantum analytical modeling of a sub-20 nm Dual Metal Double Gate (DMDG) Tunnel Field Effect Transistor (TFET) for the first time in literature. Owing to structural confinement at sub-20 nm regime, the energy states at channel are quantized and carrier propagation is regulated by quantum transport . We address such quantization aspects (viz. subband quantization, bandgap shifting, tunneling through barrier etc.) and incorporate them in analytical modeling using self-consistent solution of Schrödinger-Poisson's equation. As a result of work function difference at gate, we observe creation of quantum well , followed by a tunneling barrier, along the channel. Energy states in the quantum well are derived from Schrodinger equation, whereas, transmission coefficients are derived for each tunneling barrier. Finally, current density is obtained using ‘Landauer formula for quantum transport’. We methodically study the effects of structural confinement on device performances and observe significant shift from classical counterpart. Moreover, we note that quantization in DMDG TFET can be optimized that will lead to superior device performance. The results are verified with simulation data in each occasion to substantiate analytical models. • In this work, compact analytical model of quantum confinement in low-dimensional Dual Metal Double Gate TFET is presented. • Formation of quantum well, quantum tunneling, band gap widening effect and density of states correction are analysed. • Modelling is done based upon self-consistent Schrödinger-Poisson's solution and ‘Landauer formula for quantum transport’. • Device performances are explored in light of quantum confinement and results are validated through device simulation. • Comparative performance analysis is presented between semi-classical and quantum approach..

Improved Switching Performance of a Novel Auxiliary Gate Raised Dual Material Hetero-Dielectric Double Gate Tunnel Field Effect Transistor

Improved Switching Performance of a Novel Auxiliary Gate Raised Dual Material Hetero-Dielectric Double Gate Tunnel Field Effect Transistor

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

Investigation of the Device Electrical Parameters for Homo and Hetero Junction Based TFETs

This paper presents the analytical approximation of device physics of heterojunction based double gate (DG) Tunnel field effect transistors (TFETs) in terms of potential distribution, electron density and electron barrier tunneling. In order to improve the device performance with respect to ON current (ION), DG TFET with gate-drain overlap is developed. An asymmetric gate oxide is introduced in the gate - drain overlap region and is compared to DG TFET. The device physics and its performance characteristics are studied by using various materials, such as Si, SiGe, InAs and GaSb. The simulated results are validated against the model values. DG TFETs with gate-drain overlap offers higher tunneling probability compared to DG TFETs. Also GaSb/Si based DG TFETs with gate-drain overlap shows good performance improvement by offering higher tunneling probability which in turn offers a higher ION of 1.15 mA/μm.

Tweaking the Performance of Dopingless Nano-TFET with Misaligned Sandwiched Dual-Gate Structure

While scaling down the devices it is important not to compromise with the performance. Scaling of tunnel devices shows better performance than Field Effect Transistors (FETs). Charge Plasma based Dopingless Double Gate Tunnel Field Effect Transistor (DLDGTFET) with its various misaligned configurations are designed, discussed and analyzed in the presented work. Silicon is preferred as a choice of material. For various misalignment configurations, initially, bottom gate is shifted towards the right, then it is shifted towards left and at last bottom and top, both gates are misplaced for analyzing the device parameters, analog parameters and linearity parameters. By misalignment, it is observed that either the bottom gate is misaligned towards the right or left or both gates are being misaligned, device performance degraded. The basic structure shows the higher drain current, better drive current among other structures such as 15 μA. whereas source underlapped (SU100) structure shows the better subthreshold slope such as 20 mV/decade. But SU100 has the least amount of drive current. In the subthreshold region, BM100 has the maximum value of transconductance gain factor i.e. 104 V−1. When the bottom gate is shifted towards right i.e. for drain overlapped structure it was observed that it shows better linearity parameters and can be considered for low noise and low voltage applications.

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain underlap and a metal drain. The device is designed to address two important issues of a conventional TFET, that is, the poor ON current (ION) and the presence of ambipolar conduction. In the proposed device, the use of Ge material for the source region and a dual dielectric gate oxide enhances the ION significantly and employing metallic drain and a gate-drain underlap fully suppresses the ambipolarity conduction. This can be attributed to the formation of a Schottky barrier at channel/drain interface. Two-dimensional (2D) calibrated simulation studies have been performed using the commercial TCAD device simulator. The results have shown that the ION has improved by almost ~3 orders whereas ambipolar current is completely suppressed in the proposed device in comparison to the conventional DG-TFET. Further, it has been found that the proposed device has a subthreshold slope (SS) of 35 mV/dec, ION of ~2×10−4 A/ μm and the ION to IOFF ratio (ION/IOFF) of ~1013. The proposed device performance can be improved further by optimizing various device parameters, like underlap length etc. A flow chart mentioning the key fabrication steps has also been proposed to fabricate the proposed device.

Performance Analysis on Effect of Variation in Oxide Material of Double Gate Tunnel Field Effect Transistor

In this paper structure of Double Gate Tunnel Field Effect Transistor work to increase the efficiency of the device performance of Tunnel Field Effect Transistors making it one of the potential candidates for small scale devices. The essential point of this research work is to consider the performance analysis of the structure. This work is accomplished with the assistance of tool Cogenda TCAD version 1.9.2. The designing of the device, simulation and correlation of results have been gotten on this tool. The section gives the stream of Research Methodology and clarifies the footsteps for Design and Simulation of Double Gate Tunnel Field Effect Transistor.

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD) simulator. Here, cavity is introduced both at source and drain sides of the fixed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric to increase the capture area of biosensors. Sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) is extracted for both neutral and charged (positive/negative) biomolecules considering cavity is fully filled with different dielectric materials (k). We have reported the sensitivity with the variation in height of nanogap cavity (h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> ) for neutral biomolecules in the cavity. The sensitivity of Ge-source DMDG-TFET is found higher than C-DMDG-TFET due to more conduction at the tunnel junction. Also, the subthreshold swing (SS), transfer characteristics, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of these biosensors are reported for different k and h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> considering neutral/charged biomolecules. The sensitivity of partially filled nanogaps with biomolecules like decreasing, increasing, concave, and convex step profiles are reported for both the biosensors. The dynamic range (DR) of both the biosensors are extracted in presence of positive and negative charged biomolecules. The response time of Ge-source DMDG-TFET is reported at different k. A comparative study of proposed biosensor with other reported work is discussed. Finally, the sensitivity is extracted for DMDG-TFET considering other source material like GaAs, InAs, Si-Ge hetero stacked (HS), GaAs-InAs HS.

Suppression of Ambipolar Current and Analysis of RF Performance in Double Gate Tunneling Field Effect Transistors for Low-Power Applications

The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I_ON) than a conventional TFET via band-to-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (I_OFF) due to the large ambipolar current (I_amb). In this research work, a Si/GaAs/GaAs heterostructure DG-TFET is considered as research base for investigation of device performance.

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.