Double Gate Tunnel Field Effect Research Articles

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Impact of uniaxial strain on the electronic and transport properties of monolayer α-GeTe

Density functional theory calculations are performed to explore the electronic and transport properties of monolayer α-GeTe under uniaxial strain. It is found that monolayer α-GeTe has an indirect band gap of 1.75 eV and exhibits worthwhile anisotropy along with high electron mobility. The electron mobilities reach 1974 cm2 · V−1 · s−1 and 1442 cm2 · V−1 · s−1 along the zigzag and armchair directions, respectively. When uniaxial strain is applied, our results show an appreciable strain sensitivity of electron mobility. The electron mobility dramatically increases by an order of magnitude around a special strain due to the shifts of conduction band minimum. In addition, we also construct a double gate tunneling field effect transistor (TFET) with a channel of monolayer α-GeTe. The steeper sub-threshold swing and higher ON/OFF ratio are observed by applying tensile strain to the channel. As a result, it indicates that the appropriate strain can significantly improve the performance of α-GeTe TFETs.

Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and an underlap results in complete ambipolar suppression in the proposed TFET. A 2D calibrated simulation studies have revealed that ambipolar current suppression of ~ 5 orders, without affecting the on-state current of the device, when the gate voltage is varied between 1 V and -1 V, is achieved in the proposed device in comparison to the conventional DG-TFET. The complete ambipolar reduction is attributed to the reduced band-to-band-tunneling (BTBT) rate because of the Schottky barrier formation at the channel/drain interface. Further, the use of gate/drain underlap suppresses the ambipolarity completely in the proposed device in comparison to the conventional one. An ON current (ION) and OFF current (IOFF) ratio (ION/IOFF) of ~ 1012 with a subthreshold slope (SS) of 63 mV/decade is achieved in the proposed device. Further, the effect of change of various parameters on the performance of the proposed device has been thoroughly studied. It has been observed that the performance can be optimized further by using the optimum value of these parameters. A process flow for the fabrication of the proposed device has also been given.

An analytical approach of elimination of ambipolarity of DPDG- TFET using strained type II staggered SiGeSn heterostructure

The effect of ambipolarity puts TFET in an unfavorable position and restricts its superiority. The inclusion of a drain pocket at the drain-channel junction can prove it to be a realistic and successful way to remove the ambipolarity completely. In this paper, a 2-D analytical model has been presented for a Drain Pocket Double Gate Tunnel Field Effect Transistor (DP DG-TFET). The theoretical model agrees well with the previously reported data of Si DP DG-TFET. In this work, the SiGeSn heterostructure is used to achieve a lower bandgap and therefore to improve the tunnelling probability. A high ON current without any ambipolarity can be achieved from such type of DP DG-TFET.

Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor

Tunnel field effect transistor (TFET) has been recognized as a better candidate to replace Metal Oxide Semiconductor Field Effect Transistor (MOSFET) owing to its competence to achieve subthreshold swing (SS) less than 60 mV/decade and to reduce short channel effects (SCEs). However, certain limitations (low ON current and ambipolar conduction) need to be overcome so as to enhance the performance of TFET. In this paper, source material engineering (SME) is investigated to enhance ION, by replacing the material of the source region of conventional silicon double gate (DG) TFET by a low bandgap material Magnesium Silicide (Mg2Si). It is observed from simulation results that with Mg2Si as a source presented superior performance with reference to ION, Vth, SS, and ION/IOFF ratio as compared to the conventional Si DG-TFET. Further, reliability issues related to the temperature affectability for the electrical/analog performance of the proposed device is investigated for ambient temperature range (200 K to 400 K). The study done for temperature affectability reveals that, Shockley–Read–Hall recombination dominates in the subthreshold region and band to band tunneling (BTBT) mechanism is dominant in superthreshold region. Furthermore, as temperature is elevated from 200 K to 400 K, IOFF shows significant degradation by an order of 106. Also, it is evident that with increase in temperature threshold voltage (Vth) decreases and transconductance (gm) increases. This study will be helpful in achieving the better performance for Mg2Si source DG-TFET implemented in analog applications.

Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness

A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (LK = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (CGD). The (CGD) is proportional to dielectric constant (e) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and LK gives a low electron concentration (Q) and low dielectric constant (e) in channel/drain junction, respectively, which results in suppression of CGD. At VGS = 2 V, the CGD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The on-current (ION) of the proposed device is also measured as 2 × 10−5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (ION).

Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2, ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/μm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2-SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

Performance enhancement of triple material double gate TFET with heterojunction and heterodielectric

In this paper, we proposed a 2 dimensional model of tripple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-junction formed by germanium and silicon materials in the source-channel junction and heterodielectric gate stack is used with Silicon Dioxide (SiO2) and Hafnium Dioxide (HfO2) as dielectric materials. The electrical characteristics like surface potential, electric field, drain current and transconductance are demonstrated for the device by using commercially available 2D numerical device simulator Silvaco TCAD ATLAS. The variation of the drain currnet or ON current with the varying channel length (L), doping concentration of drain and source (NA and ND), thickness of device (tsi) and effective oxide layer thickness (tox) of the device is evaluated and presented. It is demonstrated that the proposed TM-DG TFET structure has better performance than single material and double material TFET. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio. Moreover, the influence of Germanium/Silicon hetero-junction has reduces the tunneling barrier width is exactly depicted. Hence the ON current (10−3A) of the proposed device is improved at the level of CMOS transistors.

Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon

Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon

Source/Gate Material-Engineered Double Gate TFET for improved RF and linearity performance: a numerical simulation

This work seeks to present a comparative analysis of linear and analog/RF performances of a silicon (Si)-source double gate tunnel field effect transistors (DG-TFET), germanium (Ge)-source DG-TFET and Gate Material Engineered germanium (GME-Ge)-source DG-TFET. The objective of this analysis is to probe the viability of the Ge-source-DG-TFET and GME-Ge-source-DG-TFET as possible components of RF/microwave systems vis-a-vis conventional Si-source-DG-TFETs. The Ge-source-DG-TFET has been shown to have superior performance parameters as compared to the Si-source-DG-TFET. It is realized that the GME-Ge-source-DG-TFET preserves the superior performance of the Ge-source-DG-TFET and displays improved device reliability in contrast to the latter. With these ideas in the backdrop, a study of parasitic capacitances, transconductance (gm1) and its higher order coefficients (gm2 and gm3), and signal performance metrics such as VIP2, VIP3, third-order Input Intercept Point (IIP3) and third-order Intermodulation Distortion (IMD3) sheds light on the linear performances of the three devices. Further, the analog/RF performances of the three devices are investigated through analog/RF Figures of Merit (FOM) including current gain, unilateral power gain and maximum available power gain (Gma). This analysis reveals that the GME-Ge-source-DG-TFET is suitable for high-frequency, low-power operation required in modern communication systems.

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric * * Project supported by the University Natural Science Research Key Project of Anhui Province (No. KJ2017A502), the Talents Project of Anhui Science and Technology University (No. DQYJ201603), and the Excellent Talents Supported Project of Colleges and Universities (No. gxyq2018048).

Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau–Khalatnikov (LK) equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer, ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method

SummaryTunnel field effect transistors are used for ultra‐low power application since it is challenging to operate CMOS at very low supply voltage. As tunnel field effect transistor has a very low subthreshold slope due to band to band tunneling (BTBT) mechanism, it has the potential to operate at very low operating voltage. It is necessary that the devices utilized in implantable bio‐medical applications and Internet of Everything (IoE) need to consume very low power. This work presents an analysis of Dual Material Double Gate Tunnel Field effect transistor (DMDG‐TFET). An analytical two dimensional (2D) model has been developed to obtain the analytical expressions for drain current. The 2D Poisson's equation has been used to calculate surface potential in the silicon channel using the superposition approximation, as it considers the short channel effects in the calculation of the current when compared to parabolic approximation. To validate the model, analytical results have been confirmed by comparing with the Sentaurus TCAD simulation results. A reduced subthreshold slope of 31.2 mV/decade is obtained in this paper. It shows that DMDG TFET is a promising candidate for ultra‐low power applications. The subthreshold swing obtained using superposition approximation is more optimized than that of parabolic approximation technique.

Analytical Modeling of a Triple Material Double Gate TFET with Hetero-Dielectric Gate Stack

In this paper, we propose and develop an analytical model of a Triple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-dielectric gate oxide stack comprising of SiO2 and HfO2. The two-dimensional Poisson’s equation has been solved using parabolic-approximation method to model the channel potential and electric field. Analytical model of drain current is developed by integrating the band-to-band tunneling generation rate over the channel thickness (tsi) and shortest tunneling path (\(L_{\min }\)). A Transconductance model is also developed using this drain current model. The proposed TM-DG TFET also provides better result with reference to input-output characteristics, subthreshold swing, ION/IOFF current ratio and ambipolar effect compared to the dual material double gate (DM-DG) TFET. The analytical model has been validated with the numerical data obtained from commercial TCAD software.

Impact of Pocket-Size Variation on the Performance of GaAs0.1Sb0.9/InAs Based Heterojunction Double Gate Tunnel Field Effect Transistor

Impact of Pocket-Size Variation on the Performance of GaAs_0.1Sb_0.9/InAs Based Heterojunction Double Gate Tunnel Field Effect Transistor

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement * * Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (ION) of about 0.2 mA and less leakage current (IOFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (gm), higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher fmax of 985 GHz is obtained for drain doping of 5 × 1017 cm−3 because of the reduced gate-drain capacitance (Cgd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of Cgd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values.

Enhancing analog performance and suppression of subthreshold swing using hetero-junctionless double gate TFETs

This paper proposes hetero-junctionless double gate tunnel field effect transistor (HJLDG-TFETs) for suppression of subthreshold swing (SS) using an InAs compound semiconductor material. The proposed device with high dielectric material, gives an excellent performance when InAs uses at source side. Because of low band gap of 0.36eV, it reduces the potential barrier height of source channel interface causing higher band to band tunneling. Whereas, Si at the drain side with higher band gap of 1.12eV, increasing the barrier height of drain channel interface causing lower quantum tunneling. As a result, the proposed device with high-k (HfO2) at 30 nm channel section provides a tremendous characteristics with high ION/IOFF ratio of 2×1011, a point SS of 43.30mV/decade and moderate SS of 56.75mV/decade. All the above results show that the proposed device is assured for a low power switching application. The variation in gate supply voltage also analyzed for transconductance property of the device.

Dual metal drain Ge‐source dopingless TFET with enhanced turn‐ON steep subthreshold swing and high ON‐current

A novel dopingless Ge-source dual metal drain double gate tunnel field effect transistor is presented with the help of work function engineering. Proposed device makes use of the dopingless concept, charge plasma for carrier doping concentration below the drain/source region that permits dynamic configuration by choosing suitable work function for drain/source metal electrode. In the proposed device, the n + drain region is divided into two parts of low and high work function. The work function of the metal nearest to the drain–channel junction is relatively higher than the other metal for creating a potential barrier for restricting the tunnelling of holes when the negative gate voltage is applied. By using low energy bandgap Ge material, the tunnelling probability and drive current of the device are increased. The proposed device offers high I ON/I OFF ratio (∼1013), smaller point subthreshold swing (SS) (∼31 mV/decade), average SS (∼43 mV/decade).

Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

Investigation of Ge based double gate dual metal tunnel FET novel architecture using various hetero dielectric materials

In this manuscript, Ge based dual metal double gate Tunnel Field Effect Transistor device has been investigated to overcome the challenges in conventional Si based TFET. This device gives a better drive current and an average Subthreshold slope using Ge channel. The performance analysis is done for various values of doping concentration and also for different hetero dielectric materials. It has very low leakage current (9.27 × 10−13 A/μm), a high on current (1.3 × 10−4 A/μm), giving an average Subthreshold slope of 34 mV/dec. This shows the device is better suitable for low power applications.