Double Gate Tunnel FET Research Articles

Device Reliability of Negative Capacitance Source Pocket Double Gate TFETs: A Study on Temperature and Noise Effects

Abstract This study investigates the reliability of a negative capacitance source pocket double gate tunnel field-effect transistor (NC-SP-DGTFET) by examining the effects of temperature and various noise components on its performance. The research focuses on key DC parameters, including the transfer characteristics, subthreshold swing, and the ION/IOFF ratio, evaluated across a temperature range from 250 to 450 K. Additionally, the study explores the radio-frequency performance of the device by assessing how temperature impacts transconductance (gm), cut-off frequency (fT), gate capacitance (Cgg), intrinsic delay, and the transconductance frequency product. Noise performance metrics are also analyzed, focusing on the drain current noise power spectral density (SID) and gate voltage noise power spectral density (SVG). The study considers the contributions of diffusion, generation-recombination (G-R), and flicker noise components and at 300 K, SID and SVG showed peak values of 5.08×10-26 A²/Hz and 2.67×10-16 V²/Hz, 5.73×10-18 A²/Hz and 3.22×10-10 V²/Hz, and 1.33×10-25 A²/Hz and 1.19×10-14 V²/Hz, respectively. The analysis reveals that flicker noise is predominant at lower frequencies, while diffusion noise becomes more significant at higher frequencies. However, G-R noise is the most dominant across all frequencies examined. These findings provide crucial insights for optimizing the design and performance of NC-SP-DGTFETs in low-power applications.

Design and Investigation of Gate Overlap Step Shape Double Gate (SSDG) TFET for Photosensing Applications

Design and Investigation of Gate Overlap Step Shape Double Gate (SSDG) TFET for Photosensing Applications

Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET

This research work evaluates a performance analysis of heterostructure (SiGe/Si) double gate extended source Tunnel FET (Hetero-ES-TFET) to enhance the analog performance, linearity and noise performance. At the source-channel junction, a Hetero-ES-TFET's source is extended into the channel to increase point and line tunneling in the device. The Hetero-ES-TFET exhibits a high ION/IOFF of 3.57 × 1012 and a maximum cut off frequency fT of 54.19 GHz for optimization of device structural parameters. This analysis is conducted using a calibrated SILVACO, technology computer-aided design (TCAD) simulator. The proposed structure includes evaluation of linearity and noise performance characteristics. Furthermore, a linearity analysis as a figure of merit was conducted for the proposed device under study, including different parameters such as 3rd order intermodulation distortion point (IMD3), 3rd order intermodulation intercept point (IIP3), 2nd and 3rd order voltage intercept point (VIP2 and VIP3). The proposed Hetero-ES-TFET has achieved an incredibly high ON current and low threshold voltage. The effect of increasing source width has been examined in this work while sub-threshold swing (SS) remains unchanged during the analysis. There is an improvement in threshold voltage and ION/IOFF value by using silicon-germanium (SiGe) as a source material.

Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary I ON/I OFF ratio of 2.33 × 1013, with an I OFF of 6.25 × 10−19A/µm, and decent I on of 1.46 × 10−5A/µm along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.

Miller capacitance reduction in negative capacitance TFETs

ABSTRACT A dielectric stacked hetero-gate topology is proposed to reduce the Miller capacitance in a negative capacitance double gate TFET. An analytical charge-based model is introduced for the analysis of the terminal capacitance behaviour of the device. Charge and capacitance models are developed using the surface potential modelling approach by solving the Poisson Equation. The proposed closed-form charge model is SPICE-compatible and can be used for circuit simulations. The model accuracy is validated by combining one-dimensional Landau–Khalatnikov equation with the two-dimensional simulations of the double gate stacked-hetero-gate tunnel field effect transistor. The model shows excellent agreement with device simulations. The proposed topology exhibits Miller capacitance reduction of 30% which results in the gain band width product improvement of 43% more than the stacked homo-gate counterpart.

Energy efficient artificial gustatory system for in-sensor computing

In this work, a novel bio-inspired artificial gustatory system is proposed for in-sensor neuromorphic computing. The system is demonstrated using a novel material-engineered compound-semiconductor double-gate ferroelectric tunnel FET. The behaviour of the device as a biosensor and as a spiking neuron is verified individually. Using extensive simulation in Atlas TCAD, the biosensor functionality is validated with ION sensitivity of 108. Likewise, the device shows excellent neuronal behaviour with energy consumption of 37 aJ/spike, without using any external circuitry. It also exhibits control over the spiking frequency through amplitude, frequency, and duty cycle of input synaptic current. By cascading the biosensor and neuron, a complete bio-mimicked gustatory system is designed to identify a separate pattern for different tastes. The proposed gustatory system integrates both the devices, and simultaneously performs sensing and spike encoding. The biosensor transduces the pH and dielectric constant of the target biomolecule, corresponding to gustatory neurons present in the taste buds of a biological gustatory system. The neuron performs spike encoding and acts as an input neuron in a classifying network, which corresponds to gustatory cortex of its biological counterpart. The system consumes an average power of 49.58 pW which is ∼1000 × lesser than the state-of-the-art artificial gustatory system, eliminating the need for complex hardware and exorbitant energy consumption. Therefore, the proposed gustatory system provides a highly efficient and compact solution for neuromorphic gustatory sensing and classification, with potential applications in portable, wearable, and implantable devices.

Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance

Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (I ON), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional I ON, I ON/I OFF ratio, and minimal sub-threshold swing (S) of ∼3.04 × 10−4 A μm−1, ∼1.2 × 1010, and ∼3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ∼0.75 mS/μm, ∼0.97 THz, and ∼102 GHz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ∼1.7 × 10−15 A μm−1 to 2.4 × 10−10 A μm−1 with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

This manuscript presents a pioneering study on enhancing analog and radio frequency performance through the implementation of negative capacitance source pocket double gate tunnel field-effect transistor. By integrating a ferroelectric material into the gate stack and introducing a fully depleted n-type pocket near the source/channel junction, we achieved significant enhancements in key metrics such as ON current (ION), switching ratio, subthreshold swing (SS), and various analog/RF parameters like transconductance (gm), cutoff frequency (fT) when compared to existing literature. Additionally, we extend our analysis to circuit-level applications such as inverter and 5-stage ring oscillator. Our findings reveal an impressive inverter delay of 1.09 ps with a gain of 104, as well as a ring oscillator operating at a frequency of 500 GHz. These results position the proposed device as an ideal candidate for high-speed, low-power applications.

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

This research paper investigates the application of a Double Gate (DG) Tunnel Field-Effect Transistor (DG-TFET) for the detection of cell lines derived from breast cancer tissue, namely Hs578T, MDA-MB-231, MCF-7, and T47D. The device incorporates two nanocavities positioned beneath the two gate electrodes, significantly enhancing detection capabilities. The study emphasizes the differentiation between healthy non-tumorigenic cells (MCF-10A) and breast cancer-derived cell lines by incorporating gate engineering into the TFET. Furthermore, the research explores the impact of changes in dielectric values specific to different breast malignant cell types on the biosensor's detection capabilities. Additionally, the investigation delves into the influence of variations in device geometry, including cavity dimensions and dielectric layer thickness, on critical parameters such as drain current sensitivity, transconductance sensitivity, and ION/IOFF sensitivity. Sensitivity analysis concerns drive current, ION/IOFF ratio, threshold voltage (Vth), and transconductance. The structural design of the device is tailored to facilitate array-based diagnosis and screening of cell lines derived from breast cancer tissue. This design offers several advantages, including a simplified transduction process, compatibility with CMOS processes, cost-effectiveness, reproducibility, and adjustable electrical responses. The researchers employed ATLAS, a two-dimensional (2D) device simulator from Silvaco, to model and define the device structure. The numerical simulations validate the device's performance, demonstrating favorable ON-OFF transition profiles.

A Mg2Si/Si heterojunction based dielectric modulated dopingless TFET biosensor for label free detection

In this work, we contrasted the potential of Mg2Si/Si heterojunction-based dopingless (DL) double gate tunnel field effect transistor (DGTFET) with conventional (C)-DL-DGTFET. The simulation results exhibit excellent capabilities of Mg2Si source DL-DGTFET in terms of electrical properties, that are ION, ION/IOFF, electron tunnelling rate, Vth and SS in comparison to C-DL-TFET. A remarkable improvement of 77.5 % and 81.3 % is observed while computing Vth and SS, in the case of Mg2Si source DL-DGTFET. For that reason, to avail most advantage of Mg2Si/Si heterojunction, the proposed device with similar specifications and dimensions is critically analysed for biosensing applications. Dual cavities (20 nm x 5 nm) are carved underneath gate electrodes near source channel junction to grab the biomolecules. The proposed biosensor (Mg2Si source DL-DGTFET) exhibits significant sensitivity results for both charged (deoxyribonucleic acid (DNA)) and uncharged (neutral) biomolecules. Also, we have reported an impact on biosensor sensitivity with variation in the height of nanocavity (tbio). The effect of steric hindrance on sensitivity is analysed by considering four step profiles - increasing, decreasing, convex and concave. The result reveals the competency of Mg2Si/Si heterojunction DL-DGTFET in terms of overall device sensitivity.

Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration

The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.

Thin-body effects in double-gate tunnel field-effect transistors

Scaling down the body thickness (T b) of double-gate tunnel field-effect transistors (DG-TFETs) is helpful in suppressing short-channel effects, but it may give rise to thin-body effects (TBEs). Based on 2D device simulations, this study examines the mechanisms and influences of TBEs in DG-TFETs as T b is scaled down. Differently from previous beliefs, the on-current degradation in thin-body DG-TFETs is not mainly caused by the volume effect, but rather by a newly defined TBE named lateralization effect. This is because the lateralization of tunneling direction significantly increases tunnel width, whereas the reduction of tunneling volume is quite limited due to narrow tunneling regions. To study the T b-dependence of current, therefore, the vertical tunneling has to be taken into consideration. When considered as a TBE, the fringing field effect caused by reduction in T b is not significant in degrading the on-current of thin-body DG-TFETs because the narrow tunneling regions are strongly gate-controlled. The only TBE that enhances the on-current is the coupling effect, but its role is only significant for low-bandgap bodies in which the coupling effect can efficiently promote the tunneling towards the body center. Not as previously thought that the quantum confinement effect monotonically increased, it even decreases as T b decreases down to sub-10 nm before turning to increase, thanks to the space sharing between proximate local quantum wells. A comprehensive understanding of the TBEs is useful for providing design insight, especially for determining the optimal T b to maximize the on-current.

Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET

This paper designs and implements the basic logic and universal gates based on the proposed electrically doped, configurable polarity control double gate tunnel FET (ED-CPC-DGTFET). In contrast to the CMOS and MOSFET, the primary concern of the proposed device is to overcome the transistor count needed to design logic gates. A few compact realizations of logic gates have been reported earlier using conventional double-gate TFETs. The main key to designing and implementing logic gates with the proposed structure is controlling the channel’s tunneling barrier height by altering the gate electrode work function. Additionally, abrupt interband tunneling of TFET by varying gate bias makes the device appropriate for implementing logic gates. The proposed device has a dynamic configuration that can change from n-type to p-type DGTFET by varying the bias at PG-1 and PG-2. Since lightly doped TFETs have a low ON-state current therefore, a high-k material (HfO 2 ) is employed in place of SiO 2 on top of the source side to enhance the ON-state current. Using two-dimensional simulations, the device is designed to implement logic gates with gate lengths of 50 nm and silicon body thicknesses of 10 nm (t si ). OR and AND logic gates are implemented using the n-type ED-CPC-DGTFET structure, and universal gates are implemented using the p-type variant of the proposed ED-CPC-DGTFET structure by independently biasing the top and bottom gates against various inputs.

A bio-inspired ferroelectric tunnel FET-based spiking neuron for high-speed energy efficient neuromorphic computing

In this study, a novel spiking neuron based on double-gate ferroelectric tunnel field effect transistor (DG-FE-TFET) is proposed in the 50 nm technology node. Through calibrated simulations in Atlas TCAD, it is verified that by leveraging the forward transfer characteristics, the device accurately emulates the spiking patterns exhibited by biological neurons. The device works on tunneling mechanism which ensures low voltage operation and thereby reduces overall energy consumption. The proposed neuron consumes an energy of 0.58 aJ per spike, which is 1.29, 41.38, 7.75 × 105, 12.9 × 105, 1.89 × 105, 13.79 × 106, and 7.75 × 107 times lesser than V-DGTFET, FE-JLFET, Z2-FET, DG-TFET, FD-MOSFET, Ge-MOSFET, and Si-MOSFET. Notably, the neuron operates without the need for additional reset circuitry and achieves spiking frequency of 344 GHz, which can be attributed to the sharp switching characteristics of the proposed device. This greatly simplifies implementation and facilitates a higher neuron density for energy-efficient neuromorphic chips with high-speed capabilities. Finally, based upon the proposed neuron, a multi-layer spiking neural network (SNN) is designed in Python platform. The network is implemented for signal classification with an accuracy of 84.4%.

Influence of charge traps on charge plasma-germanium double-gate TFET for RF/Analog & low-power switching applications

The device reliability on account of charge traps at the Al2O3/Ge interface is a main distress for the Ge-based Tunnel Field Effect Transistor (TFET). Here, the influence of Interface Trap Charges (ITC) on the charge plasma-based Ge-Double-Gate TFET (CP-Ge-DGTFET) and conventional Ge-DGTFET's DC, Analog/RF, and linearity characteristics have been inspected using technology-computer-aided-design (TCAD) simulations for the donor (positive) and acceptor (negative) ITC. The charge plasma concept is adopted to induce excess carrier concentration within the source region on the integration of optimum work function metal electrodes. To recognize the impact of ITC, several figures of merits have been investigated, such as transfer characteristics, electric field, transconductance, cut-off frequency, parasitic capacitance, and linearity performance parameters (VIP2, VIP3, IIP3, and IMD3). The CP-Ge-DGTFET device structure revealed superior performance and reliability in comparison to Ge-DGTFET, even under the influence of ITC at the Al2O3/Ge interface. Therefore, the CP-Ge-DGTFET device structure is a sturdy contender for Analog/RF and low-power switching applications.

Fringe-fields-modulated double-gate tunnel-FET biosensor

This paper aims to evaluate a groundbreaking bio-TFET that utilizes the fringe fields capacitance concept to detect neutral and charged biomolecules. While facilitating fabrication process and scalability, this innovative bio-TFET is able to rival the conventional bio-TFET which relies on carving cavities in the gate oxide. The cavities of the proposed device are carved in the spacers over the source region and in the vicinity of the gate metal. Inserting biomolecules in the cavities of our bio-TFET modifies the fringe fields arising out of the gate metal. As a result, these spacers modulate tunneling barrier width at the source-channel tunneling junction. We have assessed our proposed device’s DC/RF performance using the calibrated Silvaco ATLAS device simulator. For further evaluation of the reliability of our bio-TFET, non-idealities, such as trap-assisted tunneling and temperature, are also studied. The device we propose is highly suitable for biosensing applications, as evidenced by the parameters of {S}_{{I}_{ds}} = 1.21 × 103, SSS = 0.365, and {S}_{{f}_{T}} = 1.63 × 103 at VGS = 1 V.

A Paradigm Shift in Vertical Tunneling Double Gate TFET Performance: Unveiling the Implications of Spacer-Drain Overlap

A Paradigm Shift in Vertical Tunneling Double Gate TFET Performance: Unveiling the Implications of Spacer-Drain Overlap