Miller capacitance reduction in negative capacitance TFETs

Abstract

ABSTRACT A dielectric stacked hetero-gate topology is proposed to reduce the Miller capacitance in a negative capacitance double gate TFET. An analytical charge-based model is introduced for the analysis of the terminal capacitance behaviour of the device. Charge and capacitance models are developed using the surface potential modelling approach by solving the Poisson Equation. The proposed closed-form charge model is SPICE-compatible and can be used for circuit simulations. The model accuracy is validated by combining one-dimensional Landau–Khalatnikov equation with the two-dimensional simulations of the double gate stacked-hetero-gate tunnel field effect transistor. The model shows excellent agreement with device simulations. The proposed topology exhibits Miller capacitance reduction of 30% which results in the gain band width product improvement of 43% more than the stacked homo-gate counterpart.