Double Gate Tunnel FET Research Articles

RF Analysis of Double-Gate Junctionless Tunnel FET for Wireless Communication Systems: A Non-quasi Static Approach

The optimum and acceptable combination of control gate (CG) process parameters, such as dielectric materials, thickness, and metal work function for a double-gate junctionless tunnel field-effect transistor, remain a subject of great interest among researchers. We report here on the significant impact of CG process variations on the radio-frequency (RF) parameters of this device structure. Studies carried out using a non-quasi-static model with CG process variations have been analyzed for current gain (h21) and unilateral power gain with the help of a Silvaco Atlas device simulator. Systematic investigations reveal that the combination of CG process parameters, such as dielectric material (SiO2) with the thickness of 2 nm and CG metal (aluminum-〈100〉), provide the optimum RF characteristics, i.e., fT (2.9 GHz) and fmax (15 GHz), while maintaining the switching ratio (0.161 × 109), intrinsic capacitances (Cgg = 0.7 fF), and transconductance (3.8 μS) at the bias conditions of Vgs (1 V) and Vds (1 V). The results have been thoroughly interpreted from energy band diagrams and the associated band-to-band tunneling rate. The studies reported here may prove to be useful for further exploring the use of the suggested device structure for Internet of Everything communications and other related applications.

Impact of source-doping gradient in terms of lateral straggle on the performance of germanium epitaxial layer double-gate TFET

The impact of source doping gradient (SDG) in terms of lateral straggle (σ) on the performance of germanium epitaxial layer double-gate tunnel field effect transistor (ETL-DGTFET) was demonstrated by a simulation study. The non-zero tilt angle used in the ion implantation during the device fabrication process extends the implanted dopant atoms to the channel region from the source and drain which affects the performance of a device during both the ON- and OFF-states. To get a deeper insight of the impact of σ on the device performance, various DC performance parameters like Ion/Ioff ratio, average Subthreshold Slope (SSavg), and analog/RF figure of merits (FOMs) like transconductance (gm), output conductance (gds), intrinsic gain (gm/gds), parasitic capacitances and cutoff frequency (fT) were explored for σ variation from 0 to 5 nm. Circuit-level performance was also studied using an n-type ETL-DGTFET based resistive load inverter. Though the device performance is effected by the strain due to lattice mismatch between Si/Ge, it does not influence the effect of lateral straggle.

Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET

Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/RF parameters vis-a-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71 × 10−3 A/µm, ON–OFF current ratio 1011, and subthreshold swing of 45 mV/decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (gm), output conductance (gd), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (fT) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (IOFF) at elevated temperatures.

Performance Improvement of Heterojunction Double Gate TFET with Gaussian Doping

A new Ge/SiGe heterojunction double-gate tunnel field effect transistor (DGT) model with hetero dielectric gate and Gaussian doping drain region is investigated for the first time. The introduction of heterojunction with hetero dielectric will reduce band-to-band tunneling (BTBT) leakage current while maintaining high mobility to enhance drain current and transconductance characteristics of the device significantly. Along with that, the combined effect of analytical drain doping profile (Gaussian) and hetero dielectric suppresses the ambipolar behavior. Different DC characteristics of the device like energy band analysis, electric field, drain current and BTBT generation rate are analyzed for the proposed structure. RF figure of merit for the HD-HJDGT-GD is express by analyzing its transconductance (gm), cut off frequency (fT), maximum oscillation frequency (fmax), gain bandwidth product (GBP) and transconductance frequency product (TFP). The outcome of the model under study is compared with conventional DGT. It is apparent from the analysis that the recommended model has better DC and RF performance, which makes this device worth studying to be used in high-frequency applications. TCAD simulation is performed by using Sentaurus 2D device simulator from Synopsys.

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length λ which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors

In this study, we examined the influence of using hetero-gate dielectrics (HGDs) on the short-channel effects (SCEs) in scaled tunnel field-effect transistors (TFETs). For bulk TFETs, the short-channel performance is not influenced by the HGD engineering because the SCEs are caused by the tunneling at the region with negligible gate control. However, the use of the HGD increases the SCEs in double-gate TFETs because the HGD reduces the gate control on the channel. When the HGD optimized in term of on-current is used, the channel of HGD-TFETs is about 10-nm longer than that of uniform-gate dielectric TFETs to obtain similar SCEs. The SCEs in HGD-TFETs can be improved by locating the drain-side heterojunction toward the drain and/or increasing the ratio of low- and high-k equivalent oxide thicknesses. Due to the trend of scaling transistors, an appropriate design of HGD to minimize the SCEs in scaled HGD-TFETs is also crucial.

Analytical modeling of surface potential, capacitance and drain current of heterojunction TFET

This paper presents an analytical model for double-gate (DG) Heterojunction Tunnel Field Effect Transistor (H-TFET). The Poisson’s equation is solved to obtain the electrostatic potential solution which is used to drive the capacitance and drain current model. To include the impact of n-type impurity atoms in the channel region, Poisson’s equation considers the accumulation charges and ionized charges. Similarly, these charges are considered for capacitance modeling. Different III–V materials along with group-IV materials are being used to enhance the performance of H-TFET. The proposed model includes the impact of off-set between the bands due to the formation of heterojunction at the tunneling interface. The model also incorporates the influence of both the gate and the drain voltages, simultaneously. To ensure the performance of the developed model, the modeled results are validated with TCAD simulation results and a good match is obtained between them. In addition, the developed model does not include any implicit function making it SPICE-friendly for circuit designing.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Heavy ion induced single-event-transient effects in nanoscale ferroelectric vertical tunneling transistors by TCAD simulation

Tunnel field-effect transistors (TFETs) are strong candidates for ‘Internet of Things’ electronic devices, due to their ultra-low power consumption. In this work, we propose a novel nanoscale silicon-on-insulator double-gate ferroelectric tunneling field-effect transistor (SOI DG-FeTFET), and single-event-transient (SET) effects are investigated by means of two-dimensional technology computer-aided design simulations. In addition, we perform systematic analysis and comparison with a silicon-on-insulator double-gate ferroelectric field-effect transistor (SOI DG-FeET) . The simulation results show that the peak value of the drain transient current achieved by our DG-FeTFET is up to 2.72 × 10–4 A at 10 MeV·cm2 mg−1, which is much higher than the on-state current (I on) ∼ 7.63 × 10−5 A at V d = 0.5 V. Moreover, our results show that the DG-FeTFET is more susceptible to SET effects than FeFET. The results also show that the bipolar amplification effect can be neglected, and that the drift-diffusion mechanism is dominant in the carrier collection process in the DG-FeTFET. The transient responses of the single event effect are also strongly correlated with the strike location of heavy ions, with the most sensitive part being close to the area where interband tunneling occurs and the electric field is the strongest. These analyses may prove relevant for applications SOI DG-FeTFETs/FeFETs in environments where radiation is present.

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

Abstract In this work, an innovative structure of a novel double gate tunnel field-effect transistor (TFET) is proposed with a channel length of 20 nm.The gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept. The device exhibits suppressed ambipolar current, excellent subthreshold swing and good ION/IOFF ratio. The proposed structure proves to be a promising candidate for high speed applications as it shows lesser gate-capacitance than conventional stacked-oxide gate structure. The surface potential and electric field have been modelled considering the depletion regions, using 2-D Poisson's equation with appropriate boundary conditions, based on parabolic potential approximation. A semi-empirical method has been utilized to incorporate the effect of mobile charges on the device characteristics. A physics-based model for charge and terminal capacitances has been derived, following the potential model. The drain current model is able to accurately predict the ambipolar current as well as the effects of drain voltage in saturation region. Proper optimization of the device structure has been performed to derive the best desired electrical characteristics. SILVACO ATLAS simulation data have been used to validate the analytical results of the proposed structure, thereby corroborating the precision of the present analytical model. Finally, an inverter circuit has been designed in CADENCE circuit-simulation environment to justify the usage of our device in low power and high speed digital circuit applications.

2-D Analytical Model for Electrical Characteristics of Dual Metal Heterogeneous Gate Dielectric Double-Gate TFETs with Localized Interface Charges

In this paper, a 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of dual metal (DM) heterogeneous gate dielectric (HGD) double-gate (DG) tunnel field-effect transistors (TFETs) with localized interface charges have been investigated. The surface potential model has been used to derive a compact model for the electric field by including the effects of the localized charges near the source/channel junction, mobile charges in channel region and the charges in the depletion regions formed at source/channel and drain/channel junctions. The band-to-band tunneling (BTBT) generation rate has been developed by considering the effect of the electric fields at both the source/channel and drain/channel junctions. The drain current has then been derived for all gate bias (i.e. ambipolar to forward gate bias) by using the tangent line approximation method. Finally, the threshold voltage model has been developed by using the concept of shortest tunneling path of DM-HGD DG-TFET under study. The impact of localized interface charges on the drain current and threshold voltage by varying the device dimensions are also investigated. The validity of our model results are verified by numerical simulation results obtained from 2-D device simulator ATLAS™ .

Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices

This paper investigates a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance. Starting with a conventional double-gate TFET structure, the device optimization reported in this work has led to the gradual improvement in device performance in terms of higher Ion, lower Ioff, higher Ion/Ioff ratio and lower SS. The RF parameters of the optimized GOTFET, such as the mutual transconductance gm, gate-to-drain CGD, and gate-to-source CGS capacitances and unity-gain cut-off frequency fT are analyzed. We have optimized the tunnel FET device using the industry-standard $\text {synopsys}^{{\circledR }}$ TCAD tools by studying the impact of various device parameters and dimensions on performance. We demonstrated that at high negative voltages, the proposed nGOTFET would completely suppress the ambipolar behavior of the device without deteriorating the device performance. We have compared the ambipolar current Iamb, Ioff, Ion, SS with 45 nm technology MOSFET and the TFETs reported earlier in literature. For the first time, we have proposed a GOTFET which completely suppresses the ambipolar current at high negative biases, without compromising the high Ion (1.04 mA/μ m) and low Ioff (0.27 pA/μ m) and low SS (32 mV/dec) at room temperature.

Extended Source Double-Gate Tunnel FET Based Biosensor with Dual Sensing Capabilities

An extended source double-gate tunnel FET (ESDG-DMTFET) based biosensor is proposed for label free detection of biomolecules. The proposed device consists of two parallel gates with source extended into the channel so that channel overlaps the source on both sides. The cavities are carved in the gate-oxide towards drain side in order to maximize the impact of change in dielectric constant of biomolecules on the source-channel tunnelling junction leading to substantial improvement in the performance of ESDG-DMTFET. Based on 2D simulations in TCAD simulator (ATLAS), the proposed biosensor is demonstrated to achieve two order of magnitude improvement in current sensitivity and eight times higher threshold voltage sensitivity as compared to reported TFET based biosensors.

InAs/Si Hetero-Junction Channel to Enhance the Performance of DG-TFET with Graphene Nanoribbon: an Analytical Model

In this paper, a new two-dimensional analytical model for our proposed InAs/Si based double-gate dual-metal tunnel field-effect transistor (DG-TFET) with graphene nano-ribbon is presented. Incorporating group III-V material in source – channel junction, which in turn forms heterojunction results better device performance. Moreover, thin graphene nano-ribbon placed over intrinsic channel can tune the energy gap to larger extent, which supports better band-to-band (B2B) tunneling in our model. Direct tunneling model is used for Indium Arsenide (InAs), since it is direct bandgap material. Obtained Vth as 0.19 V, sub-threshold swing (SS) as 20.76 mV/decade and ION/IOFF ratio as 108 for the case of InAs/Si DG-TFET with graphene nano-ribbon shows an improvement of 48%, 36% and 10 decades respectively compared to conventional all-Si DG-TFET. Using 2-D TCAD numerical device simulator the proposed device model is designed and validated well with analytical data.

Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and an underlap results in complete ambipolar suppression in the proposed TFET. A 2D calibrated simulation studies have revealed that ambipolar current suppression of ~ 5 orders, without affecting the on-state current of the device, when the gate voltage is varied between 1 V and -1 V, is achieved in the proposed device in comparison to the conventional DG-TFET. The complete ambipolar reduction is attributed to the reduced band-to-band-tunneling (BTBT) rate because of the Schottky barrier formation at the channel/drain interface. Further, the use of gate/drain underlap suppresses the ambipolarity completely in the proposed device in comparison to the conventional one. An ON current (ION) and OFF current (IOFF) ratio (ION/IOFF) of ~ 1012 with a subthreshold slope (SS) of 63 mV/decade is achieved in the proposed device. Further, the effect of change of various parameters on the performance of the proposed device has been thoroughly studied. It has been observed that the performance can be optimized further by using the optimum value of these parameters. A process flow for the fabrication of the proposed device has also been given.

Performance enhancement of an ultra-scaled double-gate graphene nanoribbon tunnel field-effect transistor using channel doping engineering: Quantum simulation study

In this paper, new graphene nanoribbon tunnel field-effect transistors (GNRTFETs) endowed with specific doping profiles are proposed, assessed, and compared with the conventional design through a computational investigation. The used quantum simulation is based on solving self-consistently the Poisson and Schrödinger equations using the non-equilibrium Green's function formalism in the ballistic limit. The numerical study deals with GNRTFET designs with 5 nm gate length while comparing their I-V transfer proprieties, subthreshold swing, charge density, current ratio, intrinsic delay, and power-delay product. The proposed designs, which are endowed with new doping profiles, have been found efficient in mitigating the direct source-to-drain tunneling issue of ultrascaled GNR-based TFET and in improving the ambipolar behavior while boosting the performance of the GNRTFETs. As interesting results, highly improved minimum leakage current, subthreshold swing, and switching parameters have been recorded by means of the proposed channel doping engineering-based approach. The obtained substantial improvements in the performance of ultrascaled GNRTFETs make the proposed approach as a promising way for the continual shrinking of tunnel field-effect transistors (sub-5-nm) while maintaining the required high-performance.

Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor

The submitted work presents a designed and analyzed dopingless double-gate tunnel field effect transistor. In the designed dopingless structure, doping is introduced by charge plasma technique and silicon is used as a choice of material. Initially, gate misalignment was done by shifting the bottom gate away from the drain region and toward the drain region by 50% and 100% amount. Further, both gates (top and bottom) have been misaligned by 50% and 100% for analyzing the device for analog and linearity performance. Analog parameters, device parameters and linearity parameters were calculated in order to understand the device behavior. By misaligning gates, it is found that when the bottom gate is shifting away from the source region, both gates have been misaligned by 100% showing that analog and linearity performance of the devices degrades. When the bottom gate is shifted toward the source, both gates have been misaligned by 50% providing better analog and linearity performance. Among all the misaligned structures, when both gates have been misaligned by 50% gives the best result such as ON-state current, OFF-state current, ION/IOFF, and subthreshold slope are 2.3 µA, 5.07 aA, 4.5 × 1011 and 32 mV/decade respectively.

Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp+ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO2) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO2). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO2).

A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

The influence of incorporating HfO2 as a dielectric at the drain side and a silicon stack at the source side on the electrical performance of a double-gate tunnel field-effect transistor (TFET) is investigated by comparing a conventional TFET structure with four other structures in which the gate dielectric material is either homogeneous or heterogeneous while the insulator on the drain side is either SiO2 or HfO2. Moreover, a structure with a silicon source stack is proposed and the figures of merit of the resulting device are compared with other counterparts. The results of the simulations reveal that the presence of an HfO2 insulator on the drain side reduces the ambipolar conduction while the heterogeneous gate dielectric enhances the drive current and transconductance. However, the use of HfO2 slightly deteriorates the source–gate and drain–gate capacitances in comparison with the conventional TFET. Furthermore, the incorporation of a silicon source stack along with a heterogeneous gate dielectric and HfO2 insulator on the drain side leads to a higher ION/IOFF ratio, lower subthreshold slope (S), and lower ambipolar conduction in the studied TFET with channel length of 50 nm.