Digital Inverter Research Articles

Analytical modeling of III-V heterojunction source-all-around vertical tunnel FET and its inverter circuit application

Abstract This paper presents a comprehensive analytical modeling framework for the III-V heterojunction source-all-around vertical tunnel field-effect transistor (SAA V-TFET). Using Kane's model, our approach involves solving Poisson's equations to obtain a continuous surface potential profile, followed by the derivation of drain current. These models demonstrate excellent accuracy across all operating regions, precisely predicting the potential profile, output, and transfer characteristics of SAA V-TFETs. We implemented the models in MATLAB and validated them against Sentaurus TCAD simulations. Furthermore, we present a comprehensive performance analysis of SAA V-TFET-based digital inverters.

NOR Gate Based LED Inverter

In this paper, the design and simulation of the LED inverter circuit using NOR gate in Proteus software is described. The aim of the practical is to show that simple digital inverter can be created with the NOR gate which is the universal gate and the LED will be used to show that the logic circuit is working. Incidentally, to turn the NOR gate into an inverter, it simply involves linking both inputs together and that simplifies all the layout. The simulation of the circuit was done using proteus software and as the input of the NOR gate-based inverter is changed the output LED source is also changed, and the functionality of the circuit is proved. The paper includes information about control Nor Gate in inverter configuration, the significance of digital logic circuit in basic electronics, and the utility of the Proteus software within learning and prototyping settings. The outcome supports that a NOR gate can invert depicted input indication and can power an LED in a straightforward, low-priced circuit, which forms the basis of more complicated digital set of rules circuits

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

Source engineered TFET for digital inverters application

This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.

Cd0.2Zn0.8O nanowire thin film transistor for low kickback high-speed AMLCD circuit applications

This paper reports the Cd0.2Zn0.8O channel cylindrical gate-all-around nanowire thin-film transistor (CY-GAA-NWTFT) for high-speed active-matrix liquid crystal display (AMLCD) pixel circuit with minimal kickback voltage. The AC/DC, analog, and energy efficiency of this device are investigated against the variation in lateral (channel length) as well as vertical dimension (oxide thickness) using technology computer aided design (TCAD) device simulation environment. Further, the behavior of CY-GAA-TFT is crosschecked by implementing it on resistive load digital inverter circuit followed by transient analysis to calculate delay of the inverter circuit. Moreover, static analysis has been also performed to evaluate its voltage transfer curve (VTC) to derive its noise margin and voltage gain. The execution of the proposed CY-GAA-NWT device on AMLCD pixel circuit indicates tremendous improvement in performance in terms of high-speed applications and low kickback voltage.

A Comparative Analysis of VS-CNTFET and CMOS Based Inverter Circuit

This abstract delves into the comparative exploration between Carbon Nanotube Field Effect Transistors (CNTFETs) and traditional CMOS (Complementary Metal-Oxide-Semiconductor) transistors, with a specific emphasis on digital inverter circuits. Utilizing carbon nanotubes derived from the graphene allotrope, CNTFETs are introduced as a technological advancement, providing advantages such as reduced size and lower power consumption. The investigation centres on the evaluation of the Stanford model, particularly focusing on the Virtual Source Carbon Nanotube Field Effect Transistor. This specific model showcases superior performance, compact dimensions, and decreased power requirements when contrasted with silicon-based MOSFETs. The analytical process involves subjecting virtual source CNTFET inverter circuits and MOSFET-based circuits to testing via the Symica software tool, encompassing the examination of transient response, voltage transfer characteristics, and steady-state power consumption. The outcomes underscore the potential of CNTFETs as promising alternatives in the progression of digital design, offering heightened efficiency and diminished power consumption.

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

Prospects and Challenges of Different Geometries of TFET Devices for IoT Applications

Background: The applications based on IoT are nearly boundless, and the integration of the cyber world and the physical world can be done effortlessly. TFET Based IoT applications may be the future alternative to existing MOSFET-based IoT because of the faster switching speed of TFET devices. Objectives: Prospects and challenges in a simulation study of different Geometries of TFET devices for IoT Applications. Methods: In this manuscript, the detailed study of IoT evolution, IoT applications and challenges faced by IoT industries based on different TFET geometries have been elaborated and analyzed. Results: The Internet of Things (IoT) is a new prototype that provides a set of new services for new-generation technological innovations. IoT has seized the entire technological world as it can be used in every application like health, security, environmental and biomedical applications etc. The semiconductor TFET devices operating at low supply voltage and consuming the least power are most suitable for IoT applications. The devices like digital inverter, memory, adiabatic circuit, and different shaped TFET are explained as well as compared in tabular form thoroughly Conclusion: In next-generation devices, TFET can be widely used for low-power IoT applications because of the superior switching characteristics performance.

Comparative analysis of ferroelectric quad-FinFET with and without Si3N4 spacer on analog/RF, linearity performance and digital inverter application with temperature variation

The article presents a comparative study on the performance of a ferroelectric quad-FinFET (Fe-QFinFET) with and without the implementation of Si3N4 spacer for different temperature variations by integrating the temperature-dependent Landau-coefficients into the 3D TCAD simulator. The drain current enhances in the subthreshold region while it decreases in the superthreshold region as the temperature is increased. The analog/RF parameters are enhanced at lower temperatures with the spacer dielectric. However, the Fe-QFinFET with spacer have incurred an expense in the form of a substantially high gate capacitance. A digital inverter is used to analyse the circuit performance of the Fe-QFinFET.

Engineering negative differential resistance in negative capacitance Quad-FinFET

In this work, a systematically analysis of the Negative Capacitance (NC) Quad-FinFET structure is carried out where we determine the optimal FE layer thickness that enables hysteresis-free transfer characteristics. However, negative differential resistance (NDR) is introduced along with the increased FE-layer thickness, which is not desirable for application in analogcircuits. Through the implementation of an asymmetric drain length extension and a high-k Si3N4 spacer, negative differential resistance (NDR) can be mitigated. In addition, the relatively poor analog performance generally seen in conventional FinFET structures are overcome in the drain engineered NC Quad-FinFET structure with gate spacer resulting in significant improvement in performance parameters such as transconductance, output conductance and intrinsic gain. The integration of NC Quad-FinFET as a digital inverter is carried out where the circuit propagation delay is decreased by 27.65% with drain length extension and inclusion of Si3N4 spacer. Thus, through these device optimization techniques, the NC Quad-FinFET structure shows significant improvement in both analog and digital device performance parameters.

Trap sensitivity of splitted source Z Shape horizontal pocket and hetero stack TFETs: a simulation study

This paper reports the trap sensitivity analysis of split source horizontal pocket Z shape tunnel field effect transistor (ZHP-TFET) and hetero stack TFET (HS-TFET) using technology computer aided design (TCAD) simulator. The sensitivity analysis elaborates the significance of ideal trap charges at the interface of oxide and semiconductor material for both acceptor and donor like traps. The trap sensitivity analysis is highlighted for variation in trap-concentrations, temperature, gate-metal work function, and peak energy position, for both the TFETs. Furthermore, we have implemented digital inverter on taking into account the interface trap charges effect. Result reveals that tarp sensitivity on various electrical parameter of HS-TFET is significantly higher than ZHP-TFET. It is seen that ZHP-TFET provides sensitivity around 11 and 33 under acceptor and donor impurities, respectively, whereas, for HS-TFET sensitivity is around 22 and 60 for acceptor and donor impurities, respectively, for wide variation in trap concentration. The voltage transfer characteristic and voltage gain of digital inverter are improved by observable amount in ZHP-TFET than HS-TFET for both donor and acceptor like trap. The noise margin of ZHP-TFET based resistive inverter comes 0.75 V, 0.73 V, and 0.77 V, while in case of HS-TFET these value noted as 0.32 V, 0.13 V and 0.37 V under consideration for no trap, acceptor trap, and donor trap, respectively.

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

A Sensor-less Surface Mounted PMSM for Electronic Speed Control in Multilevel Inverter

Recent advancements in power electronics technology evolves inverter fed electric motors. Speed signals and rotor position are essential for controlling an electric motor accurately. In this paper, the sensorless speed control of surface-mounted permanent magnet synchronous motor (SPMSM) has been attempted. SPMSM wants a digital inverter for its precise working. Hence, this study incorporates fifteen level inverter to the SPMSM. A sliding mode observer (SMO) based sensorless speed control scheme is projected to determine rotor spot and speed of the multilevel inverter (MLI) fed SPMSM. MLI has been operated using a multi carrier pulse width modulation (MCPWM) strategy for generation of fifteen level voltages. The simulation works are executed with MATLAB/SIMULINK software. The steadiness and the heftiness of the projected model have been investigated under no loaded and loaded situations of SPMSM. Furthermore, the projected method can be adapted for electric vehicles.

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

Design and Analysis of Dual Input Z-Source Matrix Converter

Abstract: Series Z-Source community, connecting in helping vast o preferred concept of Z-supply dc hyperlink, changed into initially projected for boosting the output voltage of strength digital inverters. Throughout this paper, that idea is prolonged on a three-section oblique matrix converter. The converter relies upon at the ultra-sparse matrix topology characterised via way of means of the minimal vary of semiconductor switches. The collection Z-supply community is positioned among the three-transfer enter rectifier level and moreover the six-transfer output electric converter level, in both the wonderful or terrible rail. A short shoot-via nation produces the voltage raise. Associate in Nursing optimum pulse breadth modulation approach is advanced for better boosting capability of the converter and decrease of transfer losses. A evaluation is made among the matrix converters mistreatment collection and standard cascade Zsource networks. The inpouring modern-day and Z-supply capacitor’s voltage are decreased in the collection Z-supply matrix converter.

Enhancing the On/Off Current Ratio in Single-Molecule FET via Destructive Quantum Interference

We investigate through atomistic calculation the electronic structure and transport properties of 3-phenylethynylene (OPE3), 7-phenylvynylene (OPV7), and [3, 3]paraCyclophane (pCp)-based molecules. We reveal and analyze the Destructive Quantum Interference (DQI) phenomenon for the pCp single-molecule junction. The provided explanation of DQI via the dominant concurrence of inter-orbital and intra-orbital interference may support DQI engineering through the chemical synthesis of ad hoc molecular channel. Furthermore, we propose a Back gate Biasing-based method for the ON/OFF CUrrent Ratio Enhancement of the single-molecule Field-Effect transistor via the control of DQI (BBB-CURE-DQI). As an important outcome of the proposed method, an ON/OFF current ratio of 103 is achieved for pCp single-molecule FET. This value is orders of magnitude larger than typical values presented in the literature. The benefit of the DQI and the effectiveness of the BBB-CURE-DQI method are finally demonstrated at the circuital level by SPICE simulations of digital inverters implemented with the investigated molecules. Our analysis and results motivate the importance of future research investment for DQI manipulation via chemical synthesis and successive control to enable single-molecule FET-based nanocomputing applications.

Electromagnetic Radiation Mechanism Analysis and Field Strength Prediction of an Elementary Digital Inverter with Cables

In this paper, common mode (CM) and differential mode (DM) far-field radiation models of a typical digital inverter with cables are built up to predict electromagnetic field strength and analyze field characteristics. The CM current model and its analyses are based on the imbalance difference method. It is found out that the voltage between the drain and the source electrodes of upper transistor is the key equivalent source of electromagnetic interference (EMI). Far-field radiation strength of the digital inverter in free space is predicted by using the asymmetrical antenna radiation method and current loop radiation method. The accuracy of these methods is verified by the CST electromagnetic simulation results in the frequency range from 1 MHz to 400 MHz. Furthermore, the radiation models are improved by using the mirror method, which enables to include the reflection effect of the metal ground plane at the electromagnetic compatibility (EMC) test site. Both the results of measurements in a semi-anechoic chamber and the simulation results confirm the proposed electromagnetic radiation prediction method.

Anisotropic Carrier Mobility from 2H WSe2.

Transition metal dichalcogenides (TMDCs) with 2H phase are expected to be building blocks in next-generation electronics; however, they suffer from electrical anisotropy, which is the basics for multi-terminal artificial synaptic devices, digital inverters, and anisotropic memtransistors, which are highly desired in neuromorphic computing. Herein, the anisotropic carrier mobility from 2H WSe2 is reported, where the anisotropic degree of carrier mobility spans from 0.16 to 0.95 for various WSe2 field-effect transistors under a gate voltage of -60V. Phonon scattering, impurity ions scattering, and defect scattering are excluded for anisotropic mobility. An intrinsic screening layer is proposed and confirmed by Z-contrast scanning transmission electron microscopy (STEM) imaging to respond to the electrical anisotropy. Seven types of intrinsic screening layers are created and calculated by density functional theory to evaluate the modulated electronic structures, effective masses, and scattering intensities, resulting in anisotropic mobility. The discovery of anisotropic carrier mobility from 2H WSe2 provides a degree of freedom for adjusting the physical properties of 2H TMDCs and fertile ground for exploring and integrating TMDC electronic transistors with better performance along the direction of high mobility.

Control of Charge Transport Properties in Molybdenum Diselenide Field-Effect Transistors for Enhanced Noise-Margin and Inverter Characteristics

Ambipolar field-effect transistor (FET) capable of transporting both holes and electrons has the advantage of operating as both p-type and n-type with a single device depending on the voltage bias condition. Among transition metal dichalcogenides (TMDs), molybdenum diselenide (MoSe₂), which has ambipolar properties, exhibits n-type dominant electrical characteristics. As a result, a digital inverter implemented only using pristine MoSe₂ FETs exhibited asymmetric and limited output swing characteristics because of the difficulty in pull-up operation. Therefore, a method for improving the p-type characteristics of MoSe₂ is needed to implement a complementary metal–oxide–semiconductor (CMOS)-like digital inverter using only MoSe₂. In this study, an n-type dominant MoSe₂ FET was adjusted to have p-type dominant characteristics through annealing process. Raman spectroscopy was used to compare the transistor with previous studies. Statistical analysis showed that the charge transport behavior was reproduced in multiple devices. The p-type enhanced MoSe₂ FET was applied as a pull-up transistor of a digital inverter to present the practicality of the annealing process to improve the p-type characteristics of the MoSe₂ FET. Eventually, a more symmetrical output swing and improved noise margin were achieved compared to a digital inverter composed of only n-type dominant MoSe₂ FETs.