Source engineered TFET for digital inverters application

Abstract

This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.