Trap sensitivity of splitted source Z Shape horizontal pocket and hetero stack TFETs: a simulation study

Abstract

This paper reports the trap sensitivity analysis of split source horizontal pocket Z shape tunnel field effect transistor (ZHP-TFET) and hetero stack TFET (HS-TFET) using technology computer aided design (TCAD) simulator. The sensitivity analysis elaborates the significance of ideal trap charges at the interface of oxide and semiconductor material for both acceptor and donor like traps. The trap sensitivity analysis is highlighted for variation in trap-concentrations, temperature, gate-metal work function, and peak energy position, for both the TFETs. Furthermore, we have implemented digital inverter on taking into account the interface trap charges effect. Result reveals that tarp sensitivity on various electrical parameter of HS-TFET is significantly higher than ZHP-TFET. It is seen that ZHP-TFET provides sensitivity around 11 and 33 under acceptor and donor impurities, respectively, whereas, for HS-TFET sensitivity is around 22 and 60 for acceptor and donor impurities, respectively, for wide variation in trap concentration. The voltage transfer characteristic and voltage gain of digital inverter are improved by observable amount in ZHP-TFET than HS-TFET for both donor and acceptor like trap. The noise margin of ZHP-TFET based resistive inverter comes 0.75 V, 0.73 V, and 0.77 V, while in case of HS-TFET these value noted as 0.32 V, 0.13 V and 0.37 V under consideration for no trap, acceptor trap, and donor trap, respectively.