Digital Delta-sigma Modulator Research Articles

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

The divider controller in a conventional phase-locked loop fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

A low power MASH digital delta-sigma modulator with accurate output average value

This paper presents a modified Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM). The proposed structure has an accurate mean value and efficient randomization for all input values to reduce the spurious tones. In addition, the proposed MASH based Sigma Delta modulator has less hardware complexity and power consumption compared to conventional structures. The Verilog HDL-based simulations and experimental implementation on FPGA have been used to verify the randomization efficiency of the proposed structure. Power consumption and hardware complexity are verified by post-synthesis simulations. The randomization efficiency of the proposed MASH DDSM is also verified by phase noise simulation of the fractional-N frequency synthesizer.

Analysis of First- and Second-Order Digital DS Modulator Used in Fractional-N PLLs

In this paper, we analyze for the first time behavior in the time domain of the accumulated quantization error induced by the first- and second-order digital DeltaSigma modulator (DSM). The DSM is adopted in fractional-N PLLs to dither frequency division factor. From the analysis, difference in behavior of the accumulated quantization error in the two cases is clearly explained. Furthermore, by mean of this, the reason of using second-order DSM is required for the calibration loop of digital/time converter canceling the quantization error is revealed. It also explains why there is variation in convergence time even with the second-order DSM when fractional part of the division factor changes.

Power optimisation of single phase clocked feedback D flip-flop for CDMA

ABSTRACT A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement.

The Design and Analysis of Single-bit Ternary Band-pass Digital Filter: Design and Analysis of Single-bit Ternary Band-pass Digital Filter

Recently, various general purpose sigma-delta modulation based general purpose DSP algorithms have been reported that possess simpler multiplier complexity, lower power consumption and less chip area features .Here in exploration, our goal is to carry on designing a ternary-bit DSP algorithm in which significant design element is a sigma delta modulator. The formation sigma - delta (SDM) has an amount of very pleasant and attractive possessions and inborn linearity by reason of which extensively consumed in communication systems. Signal is sampled more than that of Nyquist rate commonly word used oversampling and classically have a very short word length (i-e one-bit, binary or ternary) in sigma delta modulation technique. In this paper the design and simulation of ternary Band pass digital filter using sigma-delta modulation done in Mat-lab at different over-sampling ratio and compare it to multi-bit Band pass digital filter.

Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer

A Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM) is commonly employed as the divider controller in a fractional-N frequency synthesizer. Previous work has considered a time-varying pattern of spurious tones, called wandering spurs, which originate in the DDSM. Two cases have been considered, namely when the fractional part of the division ratio is (i) close to zero or (ii) close to a simple fraction. In both cases, the wandering spur pattern is independent of the initial state of the modulator. This brief considers a third case where the pattern of wandering spurs depends explicitly on the initial state. The phenomenon is explained analytically and simulation results are presented. Theoretical predictions are confirmed with spectral measurements from a representative commercial monolithic fractional-N frequency synthesizer.

Analysis of Wandering Spur Patterns in a Fractional-$N$ Frequency Synthesizer With a MASH-Based Divider Controller

The Multi-stAge noise SHaping Digital Delta-Sigma Modulator (MASH DDSM), which is commonly used as a divider controller in a fractional- $N$ frequency synthesizer, can produce a time-varying periodic pattern of tones in the output spectrum of the synthesizer; these are known as wandering spurs. In this work, a detailed analysis of the cause of wandering spur patterns in a MASH 1-1-1 DDSM-based fractional- $N$ frequency synthesizer, supported by experimental measurements, is presented.

MASH DDSM with Negative Feedback

This paper proposes a Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with negative feedback to acquire the maximum sequence length. The mathematical analysis shows that the sequence length is [Formula: see text], which is not affected by the input values and initial conditions, where [Formula: see text] is the smallest prime number above the quantization interval [Formula: see text], and [Formula: see text] is the order of the MASH DDSM. Moreover, the influence of the negative feedback on the input range is analyzed. Finally, the simulations and experiments are performed to verify the theoretical analysis.

An All-Digital Low-Noise Switching DC–DC Buck Converter Based on a Multi-sampling Frequency Delta-Sigma Modulation with Enhanced Light-Load Efficiency

This paper presents an all-digital technique to control DC–DC switching buck converters for noise-sensitive low-power applications. The controller is designed based on a multi-sampling frequency digital delta-sigma modulator, whose sampling frequency is adjusted according to the load current. The proposed controller demonstrates the efficiency performance of the digital pulse-width modulation controller counterpart at heavy load while reducing output spikes by 37 dB without any additional processing. At light load, the controller scales down the switching frequency by scaling down delta-sigma modulator sampling frequency. Consequently, light-load efficiency is improved by more than 40% compared to its fixed frequency counterpart. In particular, the proposed solution adopts a unity-gain signal-transfer function delta-sigma modulator that avoids excess phase in the control loop. The proposed technique is compact, scalable and compatible with the standard digital CMOS implementation. Experimental and simulation results characterizing the proposed solution are provided.

Influence of LFSR Dither on the Periods of a MASH Digital Delta–Sigma Modulator

This brief shows that applying a linear feedback shift register (LFSR) dither to a digital delta–sigma modulator (DDSM) cannot always increase its fundamental period. For some DDSMs, the LFSR dither may reduce its period in some cases, instead of increasing it, which worsens the output spectrum. Hence, this brief calculates the dithered DDSM’s period and analyzes the influence of LFSR dither on the period. Furthermore, for this kind of DDSM, this brief explains how to add the LFSR dither to increase the period for a full input range. Finally, the experiment is performed to confirm the analysis.

Wood receives FEED contract from IRPC for ‘world-scale’ Thai paraxylene plant

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158 GHz to 5.133 GHz. Phase noise of the LC VCO at 1 MHz offset frequency is −123.0 dBc/Hz and −116.8 dBc/Hz for carrier signal frequency of 2.158 GHz and 5.133 GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14 mW from a 1.2 V power supply and the fractional-N PLL has been implemented in 0.13 μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825 μs and the fractional-N PLL is locked within 4 μs considering the worst case coarse tuning condition.

A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Frequency Synthesizers

Fractional- $N$ frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional- $N$ frequency synthesizers.

Algebraic Operations on Delta-Sigma Bit-Streams

Operations in the Delta-Sigma ( Δ Σ ) domain are a broad field of research. In this article the main, focus is on applications in control systems, nevertheless the results are generally applicable for Δ Σ -signal processing ( Δ Σ SP) in other fields. As the bit-stream does not have an instantaneous value, algebraic operations cannot be executed directly. The first approaches were made in the 1980s based on small-scale integration logic chips by Kouvaras and by Lagoyannis. Further algebraic operations and other implementations were introduced by Zrilic, by Ng, by Bradshaw and by Homann. Other publications utilize complex networks and operations to achieve the desired algebraic operations. These presented operations can be divided into different operation classes by the based implementation idea. In this paper, the known algebraic operation classes are further developed and new operation classes are presented. All implementations are compared and evaluated. For linear operations in control applications, the introduced Bipolar Interpretation is best rated. It compensates for the signal offset of bipolar bit-streams and results in the best signal quality by mapping the logic values true and false of bit-stream to plus and minus one before the algebraic operation. The output of the algebraic operation is a multibit value, to achieve a bit-stream as output value a third step is taken. The result is modulated by a digital Δ Σ -modulator ( Δ Σ -M). For nonlinear operations the most universal implementation is also based on three steps. In the first stage, the bit-streams are processed with short sinc 3 filters, resulting in multibit values. This signal is processed by digital signal processing (DSP). The output stage is a Δ Σ -M. For some nonlinear algebraic operations there can be better solutions than DSP, like shown for limiting. In short, this paper gives a detailed overview about different Δ Σ SP classes for linear and nonlinear operations. Newly presented are the scaling with Bit-Stream Modification, the Bipolar Interpretation class, the nonlinear operation class based on digital signal processing (DSP), the modified multiplication based on Delta Adder and benchmarks of all presented operations.

Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit $\Delta\Sigma$ RF-DAC in 16-nm FinFET

This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.

A novel zero dead zone PFD and efficient CP for PLL applications

This work presents a new structure of Phase Frequency Detector (PFD) and an improved design of Charge Pump (CP) for Phase Locked Loop applications. The new structure of PFD can overcome the speed and dead zone limitations of the conventional PFD. The interesting advantage of this PFD is that the reset path has been eliminated. Therefore, the blind zone is free and as a result the phase noise will be reduced. The proposed PFD has very simple structure with using only 8-transistor. Furthermore, the modified design of CP uses a new linearization technique to cancel the noise folding caused by interaction between CP and digital delta-sigma modulator. The proposed circuits are utilized in a fractional-N phase locked loop (FNPLL) for the 2.4 GHz IEEE 802.11 b/g is implemented in a 0.18 µm standard CMOS technology. The proposed FNPLL consumes 10.3 mW from a 1.8 V supply and have a phase noise of ź 86.18 and ź 90.4 dBc/Hz at 10 and 100 kHz frequency offsets, respectively.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

ABSTRACTA low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

Design of an Error Output Feedback Digital Delta Sigma Modulator with In–Stage Dithering for Spur–Free Output Spectrum

Digital Delta Sigma Modulator (DDSM) is responsible for generation of spurious tones at the output of fractional n frequency synthesizer due their inherent periodicity. This results in an impure output spectrum of frequency synthesizer when they are used to generate the fractional numbers in the divider of Phase Locked Loop (PLL) based frequency synthesizer. This paper presents the design of Error – Output feedback modulator based third order Multi – stage noise Shaping (MASH) structure with lesser hardware and effective error compensation network to break the underlying periodicity of DDSM. The DDSM is also analyzed by using non-shaped, shaped and self – dithering mechanism to achieve a pure output spectrum and reduced quantization noise.

Mathematical calculation of sequence length in LFSR-dithered MASH digital delta-sigma modulator with odd initial condition

Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with linear feedback shift register (LFSR) dither and odd initial condition is analyzed mathematically to investigate its periodic behavior. We derive the nonlinear equation of the quantization error in each stage to determine the corresponding sequence length. And five useful lemmas are introduced to help cope with the complicated calculation caused by the pseudo-random dither signal.

Extending minimum sequence length invariantly to constant input for MASH 1‐1‐1 digital delta–sigma modulator

The architecture of MASH 1-1-1 digital delta–sigma modulator for lengthening minimum sequence length is proposed. The first stage of the proposed multi-stage noise-shaping (MASH) delta–sigma modulator consists of two parts for the quantisation of input and the generation of long periodic feed-forward signal. The feed-forward signal results in extending the minimum sequence length invariantly to the input of the MASH 1-1-1 delta–sigma modulator. The noise power spectrum is analysed for preserving the noise-shaping capability of the MASH architecture.

Hardware‐efficient multi‐channel digital sigma‐delta modulator

A method for implementing a hardware-efficient multi-channel digital sigma-delta modulator is presented for processing field sequential multiple inputs. Compared to a conventional one, which processes the inputs in a time-multiplexed manner without sharing integrator memory for the multiple sequential inputs, the proposed method significantly reduces the number of storage bits in the integrator memory by partially sharing the integrator memory for the inputs. Simulation results on modulator noise power spectral density and overall signal-to-noise ratio match well with those based on quantitative noise analysis.