Abstract
The divider controller in a conventional phase-locked loop fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.
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