Wood receives FEED contract from IRPC for ‘world-scale’ Thai paraxylene plant

Abstract

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158 GHz to 5.133 GHz. Phase noise of the LC VCO at 1 MHz offset frequency is −123.0 dBc/Hz and −116.8 dBc/Hz for carrier signal frequency of 2.158 GHz and 5.133 GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14 mW from a 1.2 V power supply and the fractional-N PLL has been implemented in 0.13 μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825 μs and the fractional-N PLL is locked within 4 μs considering the worst case coarse tuning condition.