Digital Delta-sigma Modulator Research Articles

Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator

This paper proposes the use of a digital ΣΔ modulator with pseudorandom variation of coefficients. The method improves PLL-based Fractional Frequency Synthesizer's performance while using a low order digital ΣΔ modulator. The time variant coefficients, in a low order digital ΣΔ modulator, significantly enlarge the pseudorandom output pattern period thus avoiding critical spur tones in the fractional synthesizer's phase-noise. Behavioral simulations let us verify that the proposed technique operates better than a higher order modulator with additive dither. With a low order ΣΔ architecture, the programmable divider phase-selection logic and frequency range of operation parameters can be relaxed.

Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity

In mixed-signal systems, nonlinear distortion due to nonideal analog circuitry can act on quantized digital sequences, giving rise to spurious tones. In this brief, generation of spurious tones in digital delta-sigma modulators, followed by memoryless nonlinearity, is investigated. Inherent modulator periodicity that persists even with the use of least-significant-bit dither is identified.

A Long Sequence Length, Reduced Complexity MASH 1-1-1 DDSM for Fractional-N Frequency Synthesizer

In this paper, a long sequence length, reduced complexity MASH 1-1-1 digital delta-sigma modulator (DDSM) suitable for fractional-N frequency synthesizer applications is presented. Good shaping of quantization noise is achieved by using the state of art MASH structure for a digital third-order delta-sigma modulator, meanwhile, the hardware required for this modulator is considerably reduced by recoding all carry output signal from accumulators. The functional operation of the modulator is confirmed by simulation.

Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input

In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

A Spur-Free MASH DDSM With High-Order Filtered Dither

A novel dithered multistage noise shaping (MASH) digital delta-sigma modulator (DDSM) that produces a spur-free output spectrum is presented. The order of the least significant bit (LSB) dither shaping can be increased to that of the modulator, without producing spurious tones. Theoretical results prove that the quantization noise is asymptotically white and uncorrelated with the input; this is corroborated by behavioral simulations.

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rd- and 2nd-order.

Noise Transfer Function Design and Optimization for Digital Sigma-Delta Audio DAC

The parameters of sigma-delta audio DAC depend mainly on digital sigma-delta modulator’s features, especially on its noise transfer function (NTF). Many methods of design and optimization of the loop filter’s coefficients in sigma-delta modulators have been proposed so far. These methods enable the designer to get suitable noise transfer functions for specific application. This paper reviews NTF design and optimization methods which are particularly useful in audio applications.

Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant.

Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs

This brief presents the analysis, design, and implementation of a multimode reconfigurable digital Sigma-Delta (ΣΔ) modulator for use in fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loops. Analysis of second-, third-, and fourth-order modulators with respect to PLL phase noise contribution in the presence of loop nonlinearities is performed. Optimal architectures in each order are found and a single reconfigurable modulator is designed and implemented on FPGA. The proposed architecture is able to cover seven different modes of operation and spans three orders, thus offering a great degree of noise-shaping flexibility suitable for multistandard wireless applications. A case study for LTE/WiMAX is further presented for demonstration.

Frequency synthesis using digital-to-frequency conversion and filtering

A novel topology for frequency synthesis using digital-to-frequency conversion and a filtering technique is presented. The implementation uses a high-order digital sigma-delta modulator to encode a DC value, which is then mapped to a corresponding frequency using a digital-to-frequency conversion algorithm. The output bit-sequence with the sigma-delta encoded frequency is then applied to a high-order phase-locked loop (PLL) behaving as a filter operating on the incoming instantaneous frequency. The theory of the proposed scheme is described and validated with simulation and experiment. A prototype board-level implementation with a sixth-order PLL was constructed and frequencies ranging from 30.5 to 44.5 MHz were experimentally generated with a 25 kHz resolution from a single 100 MHz master clock.

A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation

A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital SigmaDelta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the SigmaDelta modulator can be improved at the same time. The order of the SigmaDelta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18 mum CMOS process. The size of the chip area is 0.44 times 0.48 mm2. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.

Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM

Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs.

Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM

In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs.

Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z)=z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-L</sup> and NTF (z)=(1-z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sup> .

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This paper presents a 2.4-GHz digitally controlled oscillator (DCO). The circuit is designed using a 65-nm six-metal CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. It has a frequency range of about 200 MHz covering the 2.4-GHz ISM band, with around 5 MHz available for frequency modulation. Its frequency quantization step is approximately 20 kHz, with a digital SigmaDelta-modulator used to allow a 5-bit fractional digital control and provide an effective frequency resolution better than 1 kHz. Its free running oscillation phase noise is -125 dBc/Hz at 1 MHz frequency offset with 4.8 mA biasing current. The power consumption is adjustable from 1.8 mW to 12 mW.

Higher Order Digital Delta-Sigma Modulator with Small Fluctuation: Sliding Mode Operation Approach

A new design approach of a digital delta-sigma modulator with small output fluctuation is proposed. The digital delta-sigma modulators are used in the digital-analog converters, the fractional-N phase lock loop, etc. and its output fluctuation is one of the important performances although a higher order modulator often produces large fluctuations. In this work, the noise shaping filter of the modulator is operated so that the operating point may maintain close to a sliding plane by selecting the output value to reduce the fluctuation of the output signal. By employing the sliding plane, the degrees of the freedom of the output signal is enhanced.

Maximum Sequence Length MASH Digital Delta–Sigma Modulators

This paper presents a modified structure for the first-order digital delta-sigma modulator (DDSM) which yields the maximum sequence length (N) for all constant digital inputs and for all initial conditions. Using this structure, MultistAge noise-SHaping (MASH) DDSMs are developed which, for a constant input, always have a sequence length of Nl regardless of the initial conditions and input value, where N is the sequence length of each stage and l is the number of the first-order stages used in the MASH. The performance is confirmed mathematically, by simulation, and experimentally.

Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta–Sigma Modulator

A MASH digital delta-sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length M. The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an lth-order member of this modulator family M is for all constant inputs, and for all initial conditions, where M is the sequence length of the constituent first-order prime modulus quantizer EFMs.

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .