Differential Nonlinearity Research Articles

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

AbstractThis paper proposes a new 10‐bit 1GS/s digital‐to‐analog converter (DAC). In the proposed DAC configuration, a beneficial combination of differential resistor ladder and current sources is utilized to attain a significant reduction of the number of unit current sources. Therefore, the suggested 10‐bit DAC is constructed based on only 21 current sources and 64 unit resistors, which results in a considerable decrease regarding the occupied area and power consumption. Also, a modified 4‐bit thermometer decoder using a low number of transistors, based on SET‐RST D flip‐flops (SR‐DFFs), is offered to drive the unit current sources synchronously. The proposed DAC is simulated in 65‐nm Complementary metal oxide semiconductor (CMOS) technology. The postlayout simulation results indicate the better integral nonlinearity (INL) and differential nonlinearity (DNL) parameters than 0.3 least significant bit (LSB) and 0.6 LSB, respectively. Based on achieved results, the proposed DAC consumes 9.31 mW using a single supply voltage of 1.2 V. Moreover, the spurious‐free dynamic range (SFDR) is above 57 dB over 600‐MHz Nyquist bandwidth, by considering 0.0134 mm2 its occupied area.

A New Structure of 8-Bit 60 MS/s SAR-ADC Using a Reduced Switching Capacitor-DAC Array

This paper presents an analysis of the Reduced Switching Capacitor Digital-to-Analog Converter (RSC-DAC)-based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC). The proposed structure involves the Low voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier operators in two modes (Normal and Hold), the RSC-DAC switching energy, reduced by 93% contrast to the standard Charge Redistribution Switching Capacitor DAC (CRSC-DAC) method, and the Successive Approximation Register (SAR) control logic. The LSD-LC with pre-amplifier consists of a latch circuit and a pre-amplifier. The pre-amplifier is often used to eliminate the DC offset voltage and kickback noise without substantially weakening the Signal-to-Noise Ratio (SNR) to drive the main circuit while the latch is needed for comparison. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and effect of parasitic capacitances of the RSC-DAC are analyzed and improved by the new approach named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented in 250-nm CMOS design of the TANNER-EDA tool, consuming 1.74-mW power at 60[Formula: see text]MS/s. The proposed structure has an INL and a DNL, respectively, of +0.18/[Formula: see text] LSB and +0.11/[Formula: see text]0.05 LSB.

A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration

This paper presents a 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with foreground calibration for digital-to-analog converter (DAC) mismatch and comparator static offset errors. The proposed foreground calibration utilizes the redundancy to facilitate the detection of DAC weight errors, and compensates for deviations of offset and DAC weights from the ideal value in the analog domain respectively. Benefit from the choice of 0.3 fF unit capacitance, the calibration achieves a 90% reduction in DAC power overhead over the conventional method. The effectiveness of this method is demonstrated by simulations in which differential non-linearity (DNL) is reduced from −1.28 LSB to −0.53 LSB and integral non-linearity (INL) is reduced from 2.20 LSB to 1.08 LSB. The ADC implemented in 40 nm CMOS consumes 3.66 μW from a 1 V supply, and achieves an improved signal-to-noise and distortion ratio (SNDR) of from 59.68 dB to 66.67 dB and a figure of merit (FoM) of 2.07 fJ/conversion-step at Nyquist rate.

A Highly Linear FPGA-Based TDC and a Low-Power Multichannel Readout ASIC With a Shared SAR ADC for SiPM Detectors

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

PurposeIn parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.Design/methodology/approachVarious low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.FindingsThis paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.Originality/valueSimulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon-based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and-Hold Amplifier (SHA) to reduce the power consumption. The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter is within LSB. Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2 MHz, 1-Vp−p, diff input signal while consuming only 7.3mW power from 1.8V supply.

An 8-bit Hybrid TDC/Single-Slope ADC with an Improved Continuous-Time Comparator

Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator’s propagation delay and decreases its delay variation to 450[Formula: see text]ps. Using TSMC CMOS 130[Formula: see text]nm technology with a sampling frequency of 5.88[Formula: see text]MHz, the simulation result illustrates 788[Formula: see text][Formula: see text]W power consumption with the master clock frequency of 100[Formula: see text]MHz while an integral nonlinearity (INL) of [Formula: see text]1.41–+0.76[Formula: see text]LSB and a differential nonlinearity (DNL) of [Formula: see text]1.05–+0.05[Formula: see text]LSB is achieved in 625[Formula: see text]ps resolution. Finally, figure-of-merit (FoM) depicts 31.2[Formula: see text]fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications.

A High-Speed and Energy-Efficient Multi-Bit Cyclic ADC Using Single-Slope Quantizer for CMOS Image Sensors

This brief proposes a high-speed and power-efficient multi-bit cyclic analog-to-digital converter (MC ADC) for CMOS image sensor applications. The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage. It operates in only seven phases to resolve 13-bit, thus achieving high conversion speed. Moreover, the 4-bit SS quantizer employs a simple and power-efficient structure that includes only the analog circuits of an operational amplifier and a comparator. A test chip with the proposed MC ADC was fabricated using a 0.18-μm standard CMOS process technology. The measurement results show that the proposed MC ADC achieves a differential nonlinearity of +0.5/-0.54 LSB and an integral nonlinearity of +1.7/-2.8 LSB. In addition, the maximum signal-to-noise-and-distortion ratio and the effective number of bits are measured to be 73.14 dB and 11.86-bit, respectively. The measured power consumption per channel is only 87 μW at a sampling frequency of 781 kHz. Moreover, the figure of merit (FoM), which includes the power consumption per channel, row line time, and ADC resolution, is only 13.6 fJ/conversion, achieving the best FoM among the compared works. Therefore, the proposed MC ADC is suitable for CMOS image sensor applications requiring high conversion speed and low power consumption, such as digital single-lens reflex cameras and ultra-high-definition television broadcast cameras.

A high-precision and 10 bit two-step Time-to-Digital Converter for TOF application

A two-step high-precision Time-to-Digital Converter(TDC), integrated with a Single-Photon Avalanche Diode(SPAD), used for Time-Of-Flight(TOF) application, has been developed and tested. Time interval measurement is performed by the coarse counter and fine interpolator, which are utilized to measure the total periods and the residue time of the reference clock, respectively. Following a detail analysis of time precision and clock jitter in the two-step structure, the prototype TDC fabricated in GSMC 1P6M 0.18 µm CMOS Image Sensor(CIS) technology exhibits a Single-Shot Precision(SSP) of 11.415 ps and a dynamic range of 216.7 ns. In addition, a pixel of the chip occupies 100 μm×100 μm, and the measured Integral Nonlinearity(INL) and Differential Nonlinearity(DNL) are better than ±0.88 LSB and ±0.67 LSB, respectively. Meanwhile, the overall power consumption of the chip is 35 mW at 1.8 V power supply. Combined with these characteristics, the designed chip is suitable for TOF-based ranging applications.

A 64 × 64 SPAD Flash LIDAR Sensor Using a Triple Integration Timing Technique With 1.95 mm Depth Resolution

This paper presents a 64×64 dual mode flash LIDAR sensor that utilizes a triple integration timing technique. The sensor, fabricated in 130 nm HV CMOS, is capable of operating in both a direct time-of-flight (ToF) mode where the timestamp of the first arriving photon is recorded per-pixel, as well as a photon counting mode where the number of photons is recorded over a time interval. The timing technique utilizes both a time-to-digital converter (TDC) and a time-to-amplitude converter (TAC) with a counter measuring global clock cycles and the triple integration interpolator (TII) measuring between clock cycles. The TII uses an analog integration with an additional two reference integrations allowing the time measurement to be resistant to PVT variation and in turn, allowing the circuit to be miniaturized without causing a large timing non-uniformity across the array. Utilizing the TII, the sensor achieves a state-of-the-art timing performance, with a resolution of 13 ps (1.95 mm depth resolution), a maximum range of 220 μs (32 km), a single-shot jitter of 233 ps, and a differential non-linearity (DNL) of 6 ps (0.47 LSB). The sensor captures at a maximum frame rate of 8,300 fps and consumes 733 mW during operation. Experimental scenarios demonstrating the operation of the sensor are also provided.

Compact SPAD pixels with fast and accurate photon counting in the analog domain

A compact pixel for single-photon detection in the analog domain is presented. The pixel integrates a single-photon avalanche diode (SPAD), a passive quenching & active recharging circuit (PQARC), and an analog counter for fast and accurate sensing and counting of photons. Fabricated in a standard 0.18 µm CMOS technology, the simulated and experimental results reveal that the dead time of the PQARC is about 8 ns and the maximum photon-counting rate can reach 125 Mcps (counting per second). The analog counter can achieve an 8-bit counting range with a voltage step of 6.9 mV. The differential nonlinearity (DNL) and integral nonlinearity (INL) of the analog counter are within the ± 0.6 and ± 1.2 LSB, respectively, indicating high linearity of photon counting. Due to its simple circuit structure and compact layout configuration, the total area occupation of the presented pixel is about 1500 μm2, leading to a high fill factor of 9.2%. The presented in-pixel front-end circuit is very suitable for the high-density array integration of SPAD sensors.

An integrated 2-bit all optical analog to digital converter based on photonic crystal semiconductor optical amplifier

In this paper, by integrating InP/InGaAsP/InP Photonic crystal semiconductor optical amplifier (PhC-SOA) with photonic crystal channel drop filters (PhC-CDF), we present a novel fully integrated ultra-small low-power all-optical analog to digital converter (AO-ADC). The self-phase modulation in the PhC-SOA can shift the frequency of the Gaussian input pulse. The two output PhC-CDFs are designed in a way that appropriately codes the frequency-shifted pulse by the PhC-SOA, which consequently converts them to four desired digital output levels. The numerical results indicated that the center wavelength of an amplitude modulated Gaussian pulse with a center wavelength of 1551.228 nm, temporal pulse-width of 10.6 ps, and energy of 74.4 fJ can be shifted by 1.652 nm. This shift is accommodated by utilizing a PhC-SOA with a length of 9 µm and an injection current of 6.5 mA. The shifted pulse is then quantized and coded to the four digital levels of (00, 01, 10, 11) by two point-defect PhC-CDFs. The PhC-CDFs minimize the AO-ADC integral and differential nonlinearity (INL/DNL) errors by compensating for the effect of the nonlinear frequency shift induced by PhC-SOA. The proposed design offers a footprint of 142 µm2 AO-ADC working at 10 Gs/s.

Existence results for a coupled system of nonlinear multi‐term fractional differential equations with anti‐periodic type coupled nonlocal boundary conditions

This paper is concerned with the existence and uniqueness of solutions for a coupled system of nonlinear multi‐term fractional differential equations with anti‐periodic type coupled nonlocal boundary conditions. The existence of a unique solution is proved via Banach contraction mapping principle, while two existence results are proved by using Krasnosel'skiic̆'s fixed point theorem and Leray‐Schauder alternative. We also discuss a variant of the proposed problem involving fractional differential types nonlinearities. The obtained results are well illustrated by numerical examples.

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

A 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) <; 0.55 LSB, input-referred thermal noise of 114.5 μV-rms, and a bit error rate (BER) of better than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> . The power dissipation is 98 mW/channel.

A time-to-digital-converter utilizing bits-counters to decode carry-chains and DSP48E1 slices in a field-programmable-gate-array

This paper presents the implementation of a field-programmable-gate-array based high-resolution time-to-digital converter, which utilizes the carry-chains and the digital-signal-processor slices for time interpolating. Bits-counter decoders are employed to manage the output codes from both the carry-chains and the digital-signal-processor slices, in order to achieve a high utilization rate of the time interpolating cells. A single channel TDC has a 2.03 ps averaged bin size and a 2.8 ps single-shot precision. The differential-non-linearity (DNL) of the single channel TDC is −1.82 ps/+12.56 ps, and the integral-non-linearity (INL) is within −6.55 ps/+47.95 ps. The TDC performance can be further improved by implementing multiple chains in a single time measurement channel, and a 2.2 ps single-shot precision is obtained by employing four parallel channels to measure the same input signal. The reported TDC can achieve a better precision with less resources comparing to previous studies, therefore the reported architecture is favorable for those applications that require high resolution multichannel time measurements.

A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor.

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA.

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

Three-Step Cyclic Vernier TDC Using a Pulse-Shrinking Inverter-Assisted Residue Quantizer for Low-Complexity Resolution Enhancement

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a pulse-shrinking inverter-assisted residue quantizer (IRQ). Previous pulse-shrinking techniques suffer from a nonuniform shrink rate and time offset that slows the conversion and increases power consumption. The proposed pulse-shrinking IRQ reduces the time difference between residue signals instead of shrinking the pulse width. This approach achieves a high resolution with low power consumption and a high conversion rate. The critical tradeoff between resolution and dynamic range (DR) is addressed using a three-step cyclic conversion approach: coarse, fine, and residue quantization steps. The adverse effect of the oscillator startup time on linearity is analyzed, and a correction method is proposed using both on-chip circuit design and off-chip data processing. The proposed TDC is fabricated using a 180-nm CMOS process in a core area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The TDC can be configured into one of four resolution modes, 36, 64, 89, and 135 ps, at conversion rates of 0.82, 1.29, 1.47, and 1.86 MS/s, respectively. A wide DR of up to 179 ns is achieved. The linearity is well performed with a maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of 0.4/0.73 LSB at a conversion rate of 1.86 MS/s. An effective number of bits, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear</sub> up to 9.88-bit, and a figure-of-merit (FoM) down to 0.31 pJ/conversion are achieved by consuming 0.55 mW.

A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA

This article presents a high linearity time-to-digital converter (TDC) with tunable parameters, based on a field-programmable gate array (FPGA) device. Specifically, a nonuniform monotonic multiphase (NUMMP) method is proposed to reestablish equivalent delay units with nonuniform delay time to overcome the limitation of the intrinsic delay and the uniformity of delay element in FPGA firstly. Then, the raw data frame composed of the equivalent delay units is marked by a time scale marking (TSM) method. Thirdly, a feature extraction (FE) method is proposed to extract the marked raw data frame to form a feature frame, which can reduce the data volume by 79.1%. After that, the feature frames are decoded by a proposed coarse-fine decoding (CFD) algorithm, which can increase the decoding speed, shorten the dead time to 8 clock cycles and reduce the amount of decoding calculation by 80%. Finally, the proposed TDC has been verified with a Xilinx Kintex-7 FPGA. The measurement results demonstrate that the proposed NUMMP TDC with highly adjustable linearity and resolution has been realized. For a high linearity configuration with a LSB of 20 ps, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are only +0.06/-0.05 and +0.08/-0.15 LSB, respectively. And for a high-resolution configuration with a LSB of 1.87 ps, the root mean square (RMS) for the resolution can achieve 2.79 ps, and the values of the DNL and INL are +1.30/-0.54 and +3.51/-2.21 LSB, respectively.

A Time-to-Amplitude Converter With High Impedance Switch Topology for Single-Photon Time-of-Flight Measurement

This paper presents a novel time-to-amplitude converter (TAC) for single-photon direct time-of-flight (d-TOF) measurement. An innovative high impedance switch approach is proposed to significantly improve the stability of the integral current and to increase the swing of the timing voltage, enabling high linearity together with low power consumption on TAC. Implemented in a standard $0.18~\mu \text{m}$ CMOS technology, the TAC occupies only an area of $100~\mu \text{m}^{2}$ , featuring a compact configuration. The experimental results indicate that the presented TAC can acquire a 78 ps timing resolution in a 20 ns full-scale range (FSR) under the supply of 1.8 V. In particular, the TAC gains an excellent linearity characteristic with the very low differential nonlinearity (DNL) and integral nonlinearity (INL) within ±0.1 LSB and ±0.15 LSB, respectively. Additionally, the extremely low dynamic power consumption of $20~\mu \text{W}$ and the high pixel fill factor of 16 % are also achieved simultaneously. Thanks to the outstanding advantages of high-performance and compactness, the proposed TAC may be a promising candidate to realize high-density compact TOF-based imagers.