Three-Step Cyclic Vernier TDC Using a Pulse-Shrinking Inverter-Assisted Residue Quantizer for Low-Complexity Resolution Enhancement

Abstract

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a pulse-shrinking inverter-assisted residue quantizer (IRQ). Previous pulse-shrinking techniques suffer from a nonuniform shrink rate and time offset that slows the conversion and increases power consumption. The proposed pulse-shrinking IRQ reduces the time difference between residue signals instead of shrinking the pulse width. This approach achieves a high resolution with low power consumption and a high conversion rate. The critical tradeoff between resolution and dynamic range (DR) is addressed using a three-step cyclic conversion approach: coarse, fine, and residue quantization steps. The adverse effect of the oscillator startup time on linearity is analyzed, and a correction method is proposed using both on-chip circuit design and off-chip data processing. The proposed TDC is fabricated using a 180-nm CMOS process in a core area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The TDC can be configured into one of four resolution modes, 36, 64, 89, and 135 ps, at conversion rates of 0.82, 1.29, 1.47, and 1.86 MS/s, respectively. A wide DR of up to 179 ns is achieved. The linearity is well performed with a maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of 0.4/0.73 LSB at a conversion rate of 1.86 MS/s. An effective number of bits, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear</sub> up to 9.88-bit, and a figure-of-merit (FoM) down to 0.31 pJ/conversion are achieved by consuming 0.55 mW.