A time-to-digital-converter utilizing bits-counters to decode carry-chains and DSP48E1 slices in a field-programmable-gate-array

Abstract

This paper presents the implementation of a field-programmable-gate-array based high-resolution time-to-digital converter, which utilizes the carry-chains and the digital-signal-processor slices for time interpolating. Bits-counter decoders are employed to manage the output codes from both the carry-chains and the digital-signal-processor slices, in order to achieve a high utilization rate of the time interpolating cells. A single channel TDC has a 2.03 ps averaged bin size and a 2.8 ps single-shot precision. The differential-non-linearity (DNL) of the single channel TDC is −1.82 ps/+12.56 ps, and the integral-non-linearity (INL) is within −6.55 ps/+47.95 ps. The TDC performance can be further improved by implementing multiple chains in a single time measurement channel, and a 2.2 ps single-shot precision is obtained by employing four parallel channels to measure the same input signal. The reported TDC can achieve a better precision with less resources comparing to previous studies, therefore the reported architecture is favorable for those applications that require high resolution multichannel time measurements.