Differential Nonlinearity Research Articles

A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

This paper presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (GCO-TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes LUTs as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution. 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration. 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively.

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.

A low-power DTOF image sensor with double-frame-multiplexing mode for long-range detection

A novel time-to-digital converter (TDC) operation mode, called double-frame-multiplexing (DFM), is proposed for time-of-flight (TOF) measurements. It is based on the separate detection of the minimum distance and depth of the measured targets, which reduces the power consumption of in-pixel TDCs and expands the maximum detection distance under high resolution. A 64 × 64 direct TOF image sensor chip is fabricated in a 0.18 μm CMOS process. Driven by a 125 MHz multi-phase clock and a 50 MHz data readout clock, the chip achieves a maximum frame rate of 20 kframe/s, a maximum detection distance of 750 m (5 μs), and a maximum depth of field of 3 m (20 ns) with a temporal resolution of 1 ns. The DFM mode reduces the average power consumption to 60 mW without consideration of SPADs. The worst-case measured differential nonlinearity is −0.61/+0.69 least significant bit (LSB) and the maximum integral nonlinearity is −1.06/+0.66 LSB.

A 10-Bit 20 Channel LCD Column Driver Using Compact DAC

A 20-channel liquid crystal display (LCD) driver architecture is implemented with [Formula: see text]m CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using [Formula: see text]m CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140[Formula: see text]dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7[Formula: see text]V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is [Formula: see text]m and the settling time is [Formula: see text]s for the [Formula: see text] and 20[Formula: see text]pF driving load.

Calibration Methods for Time-to-Digital Converters.

In this paper, two of the most common calibration methods of synchronous TDCs, which are the bin-by-bin calibration and the average-bin-width calibration, are first presented and compared. Then, an innovative new robust calibration method for asynchronous TDCs is proposed and evaluated. Simulation results showed that: (i) For a synchronous TDC, the bin-by-bin calibration, applied to a histogram, does not improve the TDC's differential non-linearity (DNL); nevertheless, it improves its Integral Non-Linearity (INL), whereas the average-bin-width calibration significantly improves both the DNL and the INL. (ii) For an asynchronous TDC, the DNL can be improved up to 10 times by applying the bin-by-bin calibration, whereas the proposed method is almost independent of the non-linearity of the TDC and can improve the DNL up to 100 times. The simulation results were confirmed by experiments carried out using real TDCs implemented on a Cyclone V SoC-FPGA. For an asynchronous TDC, the proposed calibration method is 10 times better than the bin-by-bin method in terms of the DNL improvement.

Design and Implementation of Two-Stage Time-to-Digital Converter Based on Rapid Single-Flux-Quantum Circuits

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

Design and performance of a 16-channel coarse-fine TDC prototype ASIC

This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20.48μs and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW.

A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step.

Modifications of bijective S-Boxes with linear structures

Various systematic modifications of vectorial Boolean functions have been used for finding new previously unknown classes of S-boxes with good or even optimal differential uniformity and nonlinearity. In this paper, a new general modification method is given that preserves the bijectivity property of the function in case the inverse of the function admits a linear structure. A previously known construction of such a modification based on bijective Gold functions in odd dimension is a special case of the new method.

A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS

This work presents a wideband digital polar transmitter (DPTX) with an integrated capacitor-digital-to-analog converter (C-DAC)-based digital-to-phase converter (DPC). A normalized CORDIC algorithm is introduced to convert the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> baseband signals to a constant envelope to overcome the PM bandwidth expansion issue and avoid the amplitude modulation (AM)–phase modulation (PM) nonlinearity. In the DPC, the switched-capacitor DAC topology is employed for good linearity, and the eight-phase cell-reused technique is proposed to reduce the power consumption and increase the phase amplitude. Besides, the harmonic rejection technique is introduced to remove the third-/fifth-order and higher order local oscillator (LO) harmonics to maintain phase linearity. A broadband switched-transformer digital power amplifier (DPA) is adopted in this proposed DPTX for 0–18-dB deep power back-off efficiency enhancement. Implemented in 40nm CMOS, the DPTX is powered by only one 1.1-V supply and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4 \times 1.4$ </tex-math></inline-formula> mm2 die area. The DPC achieves the maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of ±1°/±0.8° and 12.7-mW power consumption at 1.5 GHz. The DPTX realizes wideband frequency coverage of 1.2–2.5 GHz with only 0.7-dB power variations. The DPTX achieves 20.1-dBm peak output power with 23.7% system efficiency at 1.5 GHz. With a 10-MHz 64-quadrature amplitude modulation (QAM) LTE signal, the DPTX achieves 15.0 dBm average output power, 15.2% system efficiency, and an error vector magnitude (EVM) of −28.6 dB at 1.5 GHz.

StarDICE

Context. The Hubble diagram of type-Ia supernovae (SNe-Ia) provides cosmological constraints on the nature of dark energy with an accuracy limited by the flux calibration of currently available spectrophotometric standards. This motivates new developments to improve the link between existing astrophysical flux standards and laboratory standards. Aims. The StarDICE experiment aims to establish a five-stage metrology chain from NIST photodiodes to stars, with a targeted accuracy of 1 mmag in griz colors. We present the first two stages, resulting in the calibration transfer from NIST photodiodes to a demonstration 150 mpixel CMOS sensor (Sony IMX411ALR as implemented in the QHY411M camera by QHYCCD). As a side-product, we provide full characterization of this camera, which we believe to be of potential interest in astronomical imaging and photometry and specifically discuss its use in the context of gravitational wave optical follow-up. Methods. A fully automated spectrophotometric bench was built to perform the calibration transfer. The sensor readout electronics was studied using thousands of flat-field images from which we derived stability, high-resolution photon transfer curves (PTC), and estimates of the individual pixel gain. The sensor quantum efficiency (QE) was then measured relatively to a NIST-calibrated photodiode, in a well-defined monochromatic light beam from 375 to 1078 nm. Last, flat-field scans at 16 different wavelengths were used to build maps of the sensor response, fully characterizing the sensor for absolute photometric measurements. Results. We demonstrated statistical uncertainty on QE below 0.001 e−/γ between 387 nm and 950 nm, the range being limited by the sensitivity decline of the tested sensor in the infrared. Systematic uncertainties in the bench optics are controlled at the level of 1 × 10−3 e−/γ. Linearity issues are detected at the level of 5 × 10−3 e−/γ for the tested camera and require further developments to fully correct. Uncertainty in the overall normalization of the QE curve (without relevance for the cosmology, but relevant to evaluate the performance of the camera itself) is 1%. Regarding the camera we demonstrate stability in steady state conditions at the level of 32.5 ppm. Homogeneity in the response is below 1% RMS across the entire sensor area. Quantum efficiency stays above 50% in most of the visible range, peaking well above 80% between 440 nm and 570 nm. Differential nonlinearities at the level of 1% are detected. A simple two-parameter model is proposed to mitigate the effect and found to adequately correct the shape of the PTC on half the numerical scale. No significant deviations from integral linearity were detected in our limited test. Static and dynamical correlations between pixels are low, making the device likely suitable for galaxy shape measurements.

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.

In this article, we present a spiking neural network (SNN) based on both SRAM processing-in-memory (PIM) macro and on-chip unsupervised learning with Spike-Time-Dependent Plasticity (STDP). Co-design of algorithm and hardware for hardware-friendly SNN and efficient STDP-based learning methodology is used to improve area and energy efficiency. The proposed macro utilizes charge sharing of capacitors to perform fully parallel Reconfigurable Multi-bit PIM Multiply-Accumulate (RMPMA) operations. A thermometer-coded Programmable High-precision PIM Threshold Generator (PHPTG) is designed to achieve low differential non-linearity (DNL) and high linearity. In the macro, each column of PIM cells and a comparator act as a neuron to accumulate membrane potential and fire spikes. A simplified Winner Takes All (WTA) mechanism is used in the proposed hardware-friendly architecture. By combining the hardware-friendly STDP algorithm as well as the parallel Word Lines (WLs) and Processing Bit Lines (PBLs), we realize unsupervised learning and recognize the Modified National Institute of Standards and Technology (MNIST) dataset. The chip for the hardware implementation was fabricated with a 55 nm CMOS process. The measurement shows that the chip achieves a learning efficiency of 0.47 nJ/pixel, with a learning energy efficiency of 70.38 TOPS/W. This work paves a pathway for the on-chip learning algorithm in PIM with lower power consumption and fewer hardware resources.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multi-coarse counters and one fine counter are combined in our TDC architecture. The calibration circuit employs a START and STOP calibration signal generator and a gain calibration circuit. Arbitrarily small time intervals can be measured by distributing the START and STOP signals on different channels. In the implementation process, the high-precision external clock produced by a Silicon Si5338 EVB board and the on-chip high-precision clock are combined to calibrate the TDC output data in real-time. The TDC is implemented on a specially designed FPGA board with a low-cost Xilinx Artix-7 35T FPGA. The measured least significant bit (LSB) is 17.9 ps and the calculated peak-to-peak differential nonlinearity (DNL) and integral nonlinearity (INL) values are 1.006 and 0.920 LSB. The root-mean-square (RMS) resolution is lower than 20 ps in continuous measurement.

A High-Resolution TDC Design Based on Multistep Fine Time Measurement by Utilizing Delay-Adjustable Looped Carry Chains on FPGAs

High-resolution and multi-channel time-to-digital converters (TDCs) are needed in many electrical application systems. A new multi-step fine time measurement method is proposed in this work, which is based on the delay-adjustable looped carry chains to obtain both high resolution and measurement precision. Each sub-step of the fine time measurement is assigned with a different measurement resolution in the descending order by dynamically configuring the delay line length. The time residue to be measured in the following sub-step becomes smaller, so that a finer resolution can be chosen. The overall oscillation number is the summation of the oscillation number of each sub-steps. The resolution of the TDC is determined by the last sub-step. So both high resolution and small oscillation number (corresponding to high measurement precision) can be obtained. The TDC circuit was implemented on Stratix III FPGA chip. Test results showed that the obtained resolution was less than 10 ps, and the measurement precision root mean square (RMS) was about 13 ps. The differential nonlinearity (DNL) error and the integral nonlinearity (INL) error were in the range of -1 least significant bit (LSB) to 1 LSB without any bin calibration. The resource cost per TDC channel includes the lookup table (LUT) cost of 1064 and register cost of 318. The obtained TDC is comprehensively good considering its low resource cost and high linearity, and it is promising for multi-channel TDC design.

A high-resolution clock phase shifter circuitry for ALTIROC

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs.

A 380-μW Electrochemical Impedance Measurement System for Protein Sensing

Diagnostic testing plays an important role in modern medicine, helping physicians make informed decisions regarding disease diagnosis and treatment. Proteins’ biomarkers are utilized to detect disease onset, progression, efficacy of medicines, and patient susceptibility to get a specific kind of disease. Electrochemical impedance spectroscopy (EIS) is likely to underpin the progressive drive toward sensitive, miniaturized, and portable biomarker detection practices. The EIS is a highly sensitive detection method adopted to find the electrical response of chemical samples by applying low amplitude ac voltages/currents with tunable frequency. Conventional EIS systems use mixers and lock-in amplifiers to find both the real and imaginary components of the complex impedance. In this article, we present a partially integrated EIS measurement system to find the impedance of a biological sample. It includes a programmable sine-wave synthesizer (SWS) block with a frequency range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$500 \mu $ </tex-math></inline-formula> Hz to 100 kHz. The implementation is based on switched-capacitor filters that adjust the cutoff frequency by changing the clock. The sample impedance is measured through mostly digital magnitude and phase-detection blocks. The proposed EIS system is realized using a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology with a 0.35-mm2 active area and 380- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power consumption. The proposed magnitude detection archives a differential nonlinearity (DNL) performance of −0.34/+0.3 LSB and an integral nonlinearity (INL) of −0.75/+2 LSB. The system is used to measure the impedance of biological samples containing tumor necrosis factor alpha (TNF- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha$ </tex-math></inline-formula> ) protein at variable concentrations.