A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS

Abstract

This work presents a wideband digital polar transmitter (DPTX) with an integrated capacitor-digital-to-analog converter (C-DAC)-based digital-to-phase converter (DPC). A normalized CORDIC algorithm is introduced to convert the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> baseband signals to a constant envelope to overcome the PM bandwidth expansion issue and avoid the amplitude modulation (AM)–phase modulation (PM) nonlinearity. In the DPC, the switched-capacitor DAC topology is employed for good linearity, and the eight-phase cell-reused technique is proposed to reduce the power consumption and increase the phase amplitude. Besides, the harmonic rejection technique is introduced to remove the third-/fifth-order and higher order local oscillator (LO) harmonics to maintain phase linearity. A broadband switched-transformer digital power amplifier (DPA) is adopted in this proposed DPTX for 0–18-dB deep power back-off efficiency enhancement. Implemented in 40nm CMOS, the DPTX is powered by only one 1.1-V supply and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4 \times 1.4$ </tex-math></inline-formula> mm2 die area. The DPC achieves the maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of ±1°/±0.8° and 12.7-mW power consumption at 1.5 GHz. The DPTX realizes wideband frequency coverage of 1.2–2.5 GHz with only 0.7-dB power variations. The DPTX achieves 20.1-dBm peak output power with 23.7% system efficiency at 1.5 GHz. With a 10-MHz 64-quadrature amplitude modulation (QAM) LTE signal, the DPTX achieves 15.0 dBm average output power, 15.2% system efficiency, and an error vector magnitude (EVM) of −28.6 dB at 1.5 GHz.