A Multimode Multi-Efficiency-Peak Digital Power Amplifier

Abstract

A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, and time interleaving (TI). The PA demonstrates six efficiency peaks and seamless efficiency curves between the peaks in the power back-off (PBO) region with the three efficiencyenhancement techniques. For the implementation of the efficient and linear Class-G technique, a linear single-supply current-reuse Class-G switch is proposed. It realizes a Class-G operation without any additional dedicated supply voltages, resulting in enhanced efficiency and reduced cost for an external power management unit (PMU). A local oscillator (LO) signal restoration technique is proposed to reduce the area and power consumption for the LO signal distribution. The prototype SCPA, fabricated in a 65-nm CMOS, generates 30-dBm peak output power (POUT) at 2.4 GHz and achieves drain efficiency (DE) (normalized DE) of 40.2% (100%), 37.9% (94.3%), 38.8% (96.3%), 36.3% (90.2%), 29.4% (73.0%), and 19.7% (48.9%) at 0-, 2.5-, 6-, 8.5-, 12-, and 18-dB PBOs, respectively. It achieves less than ±1° amplitude modulation (AM)-phase modulation (PM) distortion with a continuous-wave (CW) signal. It also demonstrates error vector magnitude (EVM) of -41.7 dB (-44.5 dB) and DE of 30.3% (36.2%) at an average output power of 19.1 dBm (23.2 dBm) for a 10-MHz 64-quadrature AM (QAM) orthogonal frequency-division multiplexing (OFDM) signal with a 10.9-dB peak-to-average power ratio (PAPR) (10-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR).