A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors

Abstract

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.