A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA.

Mojtaba Parsakordasiabi,Ricardo Carmona-Galán,Ion Vornicu,Ángel Rodríguez-Vázquez

doi:10.3390/s21010308

Mojtaba Parsakordasiabi, Ricardo Carmona-Galán + Show 2 more

Open Access

https://doi.org/10.3390/s21010308

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Abstract

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

Highlights

Time-to-Digital Converters (TDCs) play a key role in a broad range of applications that require time measurement
High-resolution TDCs are highly demanded for 3D imaging [2,3], Fluorescence Lifetime Imaging Microscopy (FLIM) [4,5], and Positron Emission Tomography (PET) [6,7]
field programmable gate array (FPGA)’s carry elements, whose intrinsic propagation delays can be used as a sort of fine time interpolator, have made FPGAs a suitable solution to implement high-resolution TDCs [8,9]

Summary

Introduction

Time-to-Digital Converters (TDCs) play a key role in a broad range of applications that require time measurement. Since only a few different phases of the main clock are usually available, the best achievable resolution in this method is limited Another time interpolator is based on the delay-line loop-shrinking technique [18]. RO-based multi-measurement TDL uses a ring oscillator to improve time resolution These methods enhance the linearity of the TDC at the expense of high resources consumption and/or additional dead-time. Won and Lee [24] improved the linearity of the TDL in FPGAs by introducing a tuned sampling pattern that selects different outputs of the carry elements as the outputs of the delay line In their proposed TDC, changing the sampling pattern requires more resources.

TDC Architecture

Measurements

Comparison

Conclusions

Methods