DG MOSFET Research Articles

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices

An approach based on neural computation to simulate the nanoscale CMOS circuits: Application to the simulation of CMOS inverter

As critical transistor dimensions scale below the 100nm (nanoscale) regime, quantum mechanical (QM) effects begin to manifest themselves and affect important device performance metrics. Therefore, simulation tools which can be applied to design nanoscale transistors in the future, require new theory and modeling techniques that capture the physics of quantum transport accurately and efficiently. In this paper, we apply an artificial neural network (ANN) to the study of the nanoscale CMOS circuits. The latter is based on the 2-D numerical non-equilibrium Green’s function (NEGF) simulation of the current–voltage characteristics of an undoped symmetric DG MOSFET. The encouraging comparisons between numerical results and ANN PSPICE simulations have indicated that the developed ANN subcircuit representation particularly suitable to be incorporated in SPICE-like tools for nanoscale CMOS circuits simulation.

A Verilog-A model of an undoped symmetric dual-gate MOSFET

Abstract. We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.

An Accurate and Computationally Efficient Method for Device Simulation with Scattering in Nanoscale Double-Gate Metal–Oxide–Semiconductor Transistors

An accurate and computationally efficient simulation method for quantum-mechanically treating dissipative electron transport in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs) has been described. Within the nonequilibrium Green function formalism (NEGF), scattering can be simply treated on the base of Büttiker probes. The probe strength is related to the low-field mobility, which depends on the electron subband and longitudinal position. Therefore, the low-field mobility for every subband at every position along the channel has been calculated using the eigenenergies and wavefunctions along the confinement direction and the Fermi level along the channel per self-consistent loop. As a result, the effect of scattering can be rigorously treated under the NEGF formalism.

Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8mV/decade was achieved with a channel thickness of 20nm.

Study of gate leakage current in symmetric double gate MOSFETs with high- κ/stacked dielectrics

Quantum confinement in the ultra-thin silicon film of Double gate SOI MOSFETs affects the gate current ( I G). In this work, a systematic study on I G in such devices for various high- κ/stacked gate dielectric material combinations with Equivalent Oxide thickness in the range of 1 to 2 nm has been carried out using a simulator developed for this purpose. The lower I G in DG devices compared to bulk devices is attributed to reduced vertical electric field and quantum confinement effects. The amount of improvement is affected by the body thickness and the thickness of the gate dielectric. With higher value of κ, the reduction in I G is even more pronounced. The gate dielectric can thus be more aggressively scaled with DG MOSFETs than with bulk-MOSFETs. It is found from our studies that Al 2O 3 is a better interfacial layer than SiO 2 and La 2O 3 is the most promising dielectric material to sustain scaling for the next decade.

GATE LENGTH SCALING AND MICROWAVE PERFORMANCE OF DOUBLE GATE NANOTRANSISTORS

A detailed analysis of static and dynamic characteristics of deep submicron double and single gate SOI MOSFETs is presented, based on 2D numerical simulations for high frequency analog applications. Results show that although DG MOSFET offers excellent performance with respect to short channel immunity and higher transconductance, it offers nearly two times the value of gate-to-source capacitance as compared to SG devices, thus limiting the cut-off frequency at higher gate voltages. At ultra short channel lengths and low gate overdrive voltages, DG devices show a significant improvement in cut-off frequency compared to SG devices, thus presenting DG nanotransistors as potential candidates for analog microwave applications.

A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$( V_ th)$</tex> , and drain-induced barrier-height lowering are numerically calculated for the device with different channel length ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> ) and the thickness of silicon film <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$( T_ si)$</tex> . Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ T_ si$</tex> should be simultaneously scaled down with respect to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> . From a practical fabrication point-of-view, a DG MOSFET with ultrathin <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ T_ si$</tex> will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ L/ T_ si geq 1$</tex> may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.

Power-area evaluation of various double-gate RF mixer topologies

We analyze the suitability of the double gate MOSFETs (DG MOSFETs) for RF-mixer applications from the point of optimizing the transconductance gain, power consumption, and area. Mixer topologies using the 0.13-μm conventional MOSFETs, simultaneously driven DG MOSFETs (SDDG) and the independently driven DG MOSFETs (IDDG) are compared using extensive device simulations. In the frequency range 1-40 GHz, our simulation results show that the mixer circuits realized using the SDDG technologies show an order of magnitude lower power-area product, for a given transconductance gain, compared to the conventional and the IDDG technologies.

Influence of Image and Exchange-Correlation Effects on Electron Transport in Nanoscale DG MOSFETs

The impact of image and many-body exchange-correlation effects on electron transport has been investigated for nanoscale double-gate MOSFETs, using the nonequilibrium Green function method. The simulations have been performed for metal gate and polysilicon gate MOSFETs. When the gate material is metal, the inclusion of image and exchange-correlation effects increases the computed drain current, particularly at high gate voltages. In the case of polysilicon gate, the computed drain current remains almost unchanged at high gate voltages because both effects cancel out. However, at low gate voltages, the drain current is decreased by including these effects. In this study, the wavefunction penetration into the gate oxide and gate electrode has also been taken into account. Clear discrepancies between the drain currents calculated with and without considering the penetration effect can be found at low gate voltages. Further, the electron occupancy of each valley type is markedly changed by including this effect.

Demonstration of Dopant Profiling in Ultrathin Channels of Vertical-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor by Scanning Nonlinear Dielectric Microscopy

We demonstrate dopant profiling in ultrathin channels (UTCs) (Tc=18–58 nm) of vertical-type double-gate metal-oxide-semiconductor field-effect-transistors (DG MOSFET) by scanning nonlinear dielectric microscopy (SNDM). The vertical UTCs were fabricated by orientation-dependent-wet etching. Using ion implantation technology and subsequent furnace annealing, n+-p junctions, which correspond to the source/drain of the vertical-type DG MOSFET, were formed in the upper part of the UTC. To improve the accuracy of the vertical dopant profile in the UTC, the cross-section of the UTC was magnified by beveling with a small angle by chemical mechanical polishing. Using such a beveled sample, the dopant depth profile in the vertical UTC has been measured by SNDM with nanometer-scale resolution. On the basis of the measurements of the dopant profile, an effective channel length for the vertical DG MOSFET has also been estimated quantitatively.

A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism

We propose a design oriented charge-based model for undoped DG MOSFETs under symmetrical operation that aims at giving a comprehensive understanding of the device from the design strategy. In particular, we introduce useful normalizations for current and charges that in turn lead to very simple relationships among the physical quantities. Finally, we emphasize on the link that exists between this approach and the EKV formalism derived for bulk MOSFETs, which in turn leads to the unique g ms/ I D design methodology for DG architectures.

Independently Driven DG MOSFETs for Mixed-Signal Circuits: Part I—Quasi-Static and Nonquasi-Static Channel Coupling

The two tightly coupled channels in independently driven double-gate (IDDG) MOSFET offer new opportunities in constructing mixed-signal circuit modules. Understanding of channel coupling in various bias and frequency regimes is imperative to conceptualize the circuit design and optimization. In Part I, we will investigate both quasi-static and nonquasi-static channel coupling in IDDG through capacitance simulation. The charge reshuffling between channels provides effective coupling at high frequency when source/drain (S/D) carriers cannot respond spontaneously to the applied gate signals, which opens up new high-frequency circuit possibilities beyond the S/D transit time set by the lithography limit. The bias and frequency regions that enhance channel coupling are identified. The transition frequency related to channel charge reshuffling is investigated for its dependence on device geometry. Operational principles and practical limitations are discussed. In Part II, we will present the circuit design examples based on the interchannel coupling.

Independently Driven DG MOSFETs for Mixed-Signal Circuits: Part II—Applications on Cross-Coupled Feedback and Harmonics Generation

Circuit applications utilizing the tight quasi-static and nonquasi-static channel coupling in independently driven double-gate (IDDG) MOSFETs are presented. The performances of cross-coupled differential amplifiers and mixers with IDDG are compared with those of the SDDG counterparts. The quasi-static coupling in IDDG increases output voltage swing and improves voltage waveform symmetry in the cross-coupled differential amplifier. The nonquasi-static coupling in IDDG provides fast feedback in the differential amplifiers, and allows higher frequencies in the input signals for harmonic generation in mixers. We have identified plausible advantages in IDDG that cannot be readily implemented by SDDG, which justifies the fabrication cost and parasitic capacitance penalty of IDDG.

Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs

A physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high- k) gate dielectrics. The resulting analytical model closely describes published numerical simulations over a wide range of device/material parameters. Exploiting the new device model, a concerted analysis combining FIBL-enhanced short-channel effects and gate direct tunneling current is performed on candidate high- k gate dielectrics to assess their overall impact on DG MOSFET scaling. It is projected that high- k gate dielectrics may extend DG MOSFET scaling beyond that with SiO 2 by 10–20% for a 2–3× smaller equivalent oxide thickness of high- k dielectrics than that of SiO 2.

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.

On the Ballistic Transport in Nanometer-Scaled DG MOSFETs

The scattering effects are studied in nanometer-scaled double-gate MOSFET using Monte Carlo simulation. The nonequilibrium transport in the channel is analyzed with the help of the spectroscopy of the number of scatterings experienced by electrons. We show that the number of ballistic electrons at the drain-end, even in terms of flux, is not the only relevant characteristic of ballistic transport. Then, the drive current in the 15-nm-long channel transistor generations should be very close to the value obtained in the ballistic limit even if all electrons are not ballistic. Additionally, most back-scattering events, which deteriorate the on current, take place in the first half of the channel and, in particular, in the first low field region. However, the contribution of the second half of the channel cannot be considered as negligible in any studied case i.e., for a channel length below 25 nm. Furthermore, the contribution of the second half of the channel tends to be more important as the channel length is reduced. So, in ultrashort-channel transistors, it becomes very difficult to extract a region of the channel, which itself determine the drive current I/sub on/.

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.

Frequency characteristics of sub-100 nm double-gate MOSFET for suppressing short channel effects

We have investigated threshold voltage for each gate length in order to find the optimum value for side gate length and side gate voltage. We find clear on–off stages according to the bias conditions of both gates when side gate voltage is above 2 V and side gate length is above 70 nm. We have obtained the minimum short channel effect for a double-gate metal oxide semiconductor field effect transistor (DG MOSFET). We know that the optimum side gate voltage for each side gate length is about 2 V in the case that the main gate length is 70 nm. The cut-off frequency value is 41.4 GHz at LSG = 70 nm. As a result, the DG MOSFET has excellent electrical characteristics and very high cut-off frequency.